View M38222M2-XXXHP_5701648.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

description the 3822 group is the 8-bit microcomputer based on the 740 fam- ily core technology. the 3822 group has the lcd drive control circuit, an 8-channel a-d converter, and a serial i/o as additional functions. the various microcomputers in the 3822 group include variations of internal memory size and packaging. for details, refer to the section on part numbering. for details on availability of microcomputers in the 3822 group, re- fer to the section on group expansion. features basic machine-language instructions ...................................... 71 the minimum instruction execution time ........................... 0.5 s (at 8 mhz oscillation frequency) memory size rom ................................................................. 4 k to 48 k bytes ram ................................................................. 192 to 1024 bytes programmable input/output ports ............................................ 49 software pull-up/pull-down resistors (ports p0-p7 except port p4 0 ) interrupts ................................................. 17 sources, 16 vectors (includes key input interrupt) timers ........................................................... 8-bit ? 3, 16-bit ? 2 serial i/o ...................... 8-bit ? 1 (uart or clock-synchronized) a-d converter ................................................. 8-bit ? 8 channels lcd drive control circuit bias ................................................................................... 1/2, 1/3 duty ........................................................................... 1/2, 1/3, 1/4 common output .......................................................................... 4 segment output ........................................................................ 32 2 clock generating circuits (connect to external ceramic resonator or quartz-crystal oscillator) power source voltage in high-speed mode .................................................. 4.0 to 5.5 v in middle-speed mode ............................................... 2.5 to 5.5 v (extended operating temperature version: 2.0 to 5.5 v, ta= C 20 to 85c 3.0 to 5.5 v, ta= C 40 to C 20c) (one time prom version: 2.5 to 5.5 v) (m version: 2.2 to 5.5 v) (h version: 2.0 to 5.5 v) in low-speed mode .................................................... 2.5 to 5.5 v (extended operating temperature version: 2.0 to 5.5 v, ta= C 20 to 85c 3.0 to 5.5 v, ta= C 40 to C 20c) (one time prom version: 2.5 to 5.5 v) (m version: 2.2 to 5.5 v) (h version: 2.0 to 5.5 v) power dissipation in high-speed mode .......................................................... 32 mw (at 8 mhz oscillation frequency, at 5 v power source voltage) in low-speed mode ............................................................ 45 w (at 32 khz oscillation frequency, at 3 v power source voltage) operating temperature range................................... C 20 to 85c (extended operating temperature version: C 40 to 85 c) applications camera, household appliances, consumer electronics, etc. fig. 1 m38224m6hxxxfp pin configuration (the pin configuration of 80d0 is same as this.) pin configuration (top view) package type : 80p6n-a (80-pin plastic-molded qfp) 3822 group mitsubishi microcomputers single-chip 8-bit cmos microcomputer s e g 8 s e g 9 p 3 4 / s e g 1 2 p 3 5 / s e g 1 3 p 0 0 / s e g 1 6 p 0 3 / s e g 1 9 p 0 4 / s e g 2 0 p 0 5 / s e g 2 1 p 0 6 / s e g 2 2 p 0 7 / s e g 2 3 p 1 1 / s e g 2 5 p 1 2 / s e g 2 6 p 1 3 / s e g 2 7 p 1 4 / s e g 2 8 p 1 5 / s e g 2 9 p 1 6 / s e g 3 0 p 1 7 / s e g 3 1 v l 1 p 6 7 / a n 7 m 3 8 2 2 4 m 6 h x x x f p p 5 7 / a d t p 5 0 / i n t 2 p 4 6 / s c l k p 4 5 / t x d p 4 3 / i n t 1 p 4 2 / i n t 0 a v s s v r e f v c c s e g 0 p4 1 / p 4 0 x in x out v ss p2 7 p2 6 p2 5 p2 4 p2 3 p2 2 p2 1 p2 0 reset p 5 1 / i n t 3 p 5 5 / c n t r 1 p 5 4 / c n t r 0 p 5 3 / r t p 1 p 5 2 / r t p 0 p 5 6 / t o u t p 1 0 / s e g 2 4 p 0 1 / s e g 1 7 p 0 2 / s e g 1 8 p 4 7 / s r d y s e g 1 0 s e g 1 1 p 3 6 / s e g 1 4 p 3 7 / s e g 1 5 p 7 0 / x c o u t p7 1 /x cin com 0 v l 3 p 6 6 / a n 6 p 6 5 / a n 5 p 6 4 / a n 4 p 6 3 / a n 3 p 6 2 / a n 2 p 6 1 / a n 1 p 6 0 / a n 0 v l 2 c o m 1 com 2 c o m 3 s e g 1 s e g 2 s e g 3 s e g 4 s e g 5 s e g 6 s e g 7 p 4 4 / r x d 1 234567891 01 1121 31 41 51 61 71 81 9202 122 2 324 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 41 4 2 43 4 4 45 4 6 47 4 8 49 5 0 51 52 53 5 4 55 56 57 5 8 5 9 6 0 61 6 2 6 3 6 4 6 5 6 6 6 7 6 8 6 9 7 0 7 1 7 2 7 3 7 4 7 5 76 7 7 78 7 9 8 0
2 single-chip 8-bit cmos microcomputer 3822 group mitsubishi microcomputers package type : 80p6s-a/80p6q-a (80-pin plastic-molded qfp) pin configuration (top view) fig. 2 m38223m4mxxxgp/m38224m6hxxxhp pin configuration 1 2 3 4 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 5 6 2 1 2 2 2 3 24 25 2 6 2 7 2 8 29 30 31 3 2 3 3 3 4 35 3 6 37 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 p 1 4 / s e g 2 8 p 1 5 / s e g 2 9 p1 6 /seg 30 p1 7 /seg 31 p4 2 /int 0 v cc x in x out v ss p2 7 p2 6 p2 5 p2 4 p2 3 p2 2 p2 1 p2 0 reset p7 0 /x cout p7 1 /x cin p4 1 / p4 0 p4 3 /int 1 s e g 1 0 p 3 5 / s e g 1 3 p 3 6 / s e g 1 4 p 3 7 / s e g 1 5 p 0 0 / s e g 1 6 p 0 3 / s e g 1 9 p 0 4 / s e g 2 0 p 0 5 / s e g 2 1 p 0 6 / s e g 2 2 p 0 7 / s e g 2 3 p 1 1 / s e g 2 5 p 1 2 / s e g 2 6 p 1 0 / s e g 2 4 p 0 1 / s e g 1 7 p 0 2 / s e g 1 8 p 1 3 / s e g 2 7 c o m 3 p 6 0 / a n 0 p 5 7 / a d t p 5 6 / t o u t p 5 4 / c n t r 0 p 5 3 / r t p 1 p 5 2 / r t p 0 p 5 1 / i n t 3 p 5 5 / c n t r 1 p 4 6 / s c l k p 4 5 / t x d p 5 0 / i n t 2 p 4 7 / s r d y p 4 4 / r x d seg 1 seg 2 s e g 3 s e g 4 s e g 6 s e g 5 s e g 7 seg 0 s e g 8 seg 9 com 2 com 1 com 0 v l3 v l 2 v l1 v r e f a v s s p 6 1 / a n 1 p 6 2 / a n 2 p 6 3 / a n 3 p 6 4 / a n 4 p 6 5 / a n 5 p 6 6 / a n 6 p 6 7 / a n 7 s e g 1 1 p 3 4 / s e g 1 2 m38223m4mxxxgp m38224m6hxxxhp
3 single-chip 8-bit cmos microcomputer 3822 group mitsubishi microcomputers functional block diagram (package type : 80p6q-a) fig. 3 functional block diagram k e y o n w a k e u p r e a l t i m e p o r t f u n c t i o n i n t 2 , i n t 3 c n t r 0 , c n t r 1 t o u t a d t i n t 0 , i n t 1 r t p 0 , r t p 1 d a t a b u s c p u a x y s p c h p c l p s r e s e tv c c v s s r e s e t i n p u t( 5 v ) ( 0 v ) r o m r a m l c d d i s p l a y r a m ( 1 6 b y t e s ) 2 5 7 13 0 i / o p o r t p 5 p 4 ( 8 ) i / o p o r t p 4 i / o p o r t p 2 p 2 ( 8 ) i / o p o r t p 0 p 0 ( 8 ) i / o p o r t p 1 p 1 ( 8 ) p 6 ( 8 ) i n p u t p o r t p 3 p 3 ( 4 ) i / o p o r t p 6 p 5 ( 8 ) i / o p o r t p 7 p 7 ( 2 ) 8 0 7 9 7 8 7 7 7 6 7 5 7 4 7 0 6 9 6 8 6 7 6 6 6 5 6 4 6 3 6 2 6 1 6 0 5 9 4 7 4 8 4 9 5 0 5 1 5 25 35 4 3 94 04 14 24 34 44 54 6 3 13 23 33 43 53 63 73 8 5 55 65 75 8 1 92 02 12 22 32 4 1 71 8 2 62 7 123 456 78 7 3 7 2 1 01 11 21 31 41 51 6 9 c l o c k g e n e r a t i n g c i r c u i t m a i n c l o c k i n p u t x i n m a i n c l o c k o u t p u t x o u t x c o u t s u b - c l o c k o u t p u t x c i n s u b - c l o c k i n p u t s i / o ( 8 ) v r e f a v s s ( 0 v ) a - d c o n v e r t e r ( 8 ) t i m e r x ( 1 6 ) t i m e r y ( 1 6 ) t i m e r 1 ( 8 )t i m e r 2 ( 8 ) t i m e r 3 ( 8 ) l c d d r i v e c o n t r o l c i r c u i t v l 1 v l 2 v l 3 c o m 0 c o m 1 c o m 2 c o m 3 s e g 0 s e g 1 s e g 2 s e g 3 s e g 4 s e g 5 s e g 6 s e g 7 s e g 8 s e g 9 s e g 1 0 s e g 1 1 x c i n x c o u t 2 8 2 9
4 single-chip 8-bit cmos microcomputer 3822 group mitsubishi microcomputers pin description table 1 pin description (1) v cc , v ss function pin name function except a port function ? lcd segment output pins power source ? apply voltage of power source to v cc , and 0 v to v ss . (for the limits of v cc , refer to recom- mended operating conditions ). v ref av ss reset x in x out v l1 C v l3 com 0 C com 3 seg 0 C seg 11 p0 0 /seg 16 C p0 7 /seg 23 p1 0 /seg 24 C p1 7 /seg 31 p2 0 C p2 7 p3 4 /seg 12 C p3 7 /seg 15 analog refer- ence voltage analog power source reset input clock input clock output lcd power source common output segment output i/o port p0 i/o port p1 i/o port p2 ? reference voltage input pin for a-d converter. ? gnd input pin for a-d converter. ? connect to v ss . ? reset input pin for active l . ? input and output pins for the main clock generating circuit. ? feedback resistor is built in between x in pin and x out pin. ? connect a ceramic resonator or a quartz-crystal oscillator between the x in and x out pins to set the oscillation frequency. ? if an external clock is used, connect the clock source to the x in pin and leave the x out pin open. ? this clock is used as the oscillating source of system clock. ? input 0 v l1 v l2 v l3 v cc voltage. ? input 0 C v l3 voltage to lcd. ? lcd common output pins. ? com 2 and com 3 are not used at 1/2 duty ratio. ? com 3 is not used at 1/3 duty ratio. ? lcd segment output pins. ? 8-bit output port. ? cmos compatible input level. ? cmos 3-state output structure. ? i/o direction register allows each port to be individually programmed as either input or output. ? pull-down control is enabled. ? 8-bit i/o port. ? cmos compatible input level. ? cmos 3-state output structure. ? i/o direction register allows each pin to be individually programmed as either input or output. ? pull-up control is enabled. ? 4-bit input port. ? cmos compatible input level. ? pull-down control is enabled. ? key input (key-on wake-up) interrupt input pins ? lcd segment output pins input port p3
5 single-chip 8-bit cmos microcomputer 3822 group mitsubishi microcomputers table 2 pin description (2) function pin name function except a port function p4 0 p4 2 /int 0 , p4 3 /int 1 p4 4 /r x d, p4 5 /t x d, p4 6 /s clk , p4 7 /s rdy p5 0 /int 2 , p5 1 /int 3 p5 2 /rtp 0 , p5 3 /rtp 1 p5 4 /cntr 0 , p5 5 /cntr 1 p5 6 /t out p5 7 /adt p6 0 /an 0 C p6 7 /an 7 p7 0 /x cout, p7 1 /x cin i/o port p4 i/o port p5 i/o port p6 i/o port p7 ? 1-bit input port. ? cmos compatible input level. ? 7-bit i/o port. ? cmos compatible input level. ? cmos 3-state output structure. ? i/o direction register allows each pin to be individually programmed as either input or output. ? pull-up control is enabled. ? 8-bit i/o port. ? cmos compatible input level. ? cmos 3-state output structure. ? i/o direction register allows each pin to be individually programmed as either input or output. ? pull-up control is enabled. ? 8-bit i/o port. ? cmos compatible input level. ? cmos 3-state output structure. ? i/o direction register allows each pin to be individually programmed as either input or output. ? pull-up control is enabled. ? 2-bit i/o port. ? cmos compatible input level. ? cmos 3-state output structure. ? i/o direction register allows each pin to be individually programmed as either input or output. ? pull-up control is enabled. ? clock output pin ? interrupt input pins ? interrupt input pins ? real time port function pins ? timer x, y function pins ? timer 2 output pins ? a-d conversion input pins ? sub-clock generating circuit i/o pins. (connect a resonator. external clock cannot be used.) input port p4 p4 1 / ? serial i/o function pins ? a-d trigger input pins
6 single-chip 8-bit cmos microcomputer 3822 group mitsubishi microcomputers part numbering fig. 4 part numbering package type fp : 80p6n-a package gp : 80p6s-a package hp : 80p6q-a package fs : 80d0 package rom number omitted in one time prom version shipped in blank and eprom version. product m3822 4 m 6 h xxx fp normally, using hyphen. when electrical characteristic, or division of identification code using alaphanumeric character C :standard d : extended operating temperature version m :m version h : h version rom/prom size 1 : 4096 bytes 2 : 8192 bytes 3 : 12288 bytes 4 : 16384 bytes 5 : 20480 bytes 6 : 24576 bytes 7 : 28672 bytes 8 : 32768 bytes the first 128 bites and the last 2 bytes of rom are reserved areas ; they cannot be used. memory type m : mask rom version e : eprom or one time prom version ram size 0 : 192 bytes 1 : 256 bytes 2 : 384 bytes 3 : 512 bytes 4 : 640 bytes 5 : 768 bytes 6 : 896 bytes 7 : 1024 bytes 9 : 36864 bytes a : 40960 bytes b : 45056 bytes c : 49152 bytes
7 single-chip 8-bit cmos microcomputer 3822 group mitsubishi microcomputers group expansion (standard, one time prom version, eprom version) mitsubishi plans to expand the 3822 group (standard, one time prom version, eprom version) as follows: memory type support for mask rom, one time prom, and eprom versions memory size rom size ............................................................. 8 k to 48 k bytes ram size ............................................................ 384 to 1024 bytes package 80p6n-a .................................... 0.8 mm-pitch plastic molded qfp 80p6s-a .................................. 0.65 mm-pitch plastic molded qfp 80p6q-a .................................... 0.5 mm-pitch plastic molded qfp 80d0 ....................... 0.8 mm-pitch ceramic lcc (eprom version) currently products are listed below. memory expansion plan remarks package product as of feb. 2002 ram size (bytes) 8192 (8062) rom size (bytes) rom size for user in ( ) 16384 (16254) fig. 5 memory expansion plan table 3 list of products m38222m2-xxxfp m38222m2-xxxgp M38222M2-XXXHP m38223m4-xxxfp m38223e4fp m38223m4-xxxgp m38223e4gp m38223m4-xxxhp m38223e4hp m38223e4fs m38227ecfp m38227echp m38227ecfs 384 80p6n-a 80p6s-a 80p6q-a mask rom version mask rom version mask rom version mask rom version one time prom version (blank) mask rom version one time prom version (blank) mask rom version one time prom version (blank) eprom version one time prom version (blank) one time prom version (blank) eprom version note: products under development or planning: the development schedule and specifications may be revised without notice. 512 80p6n-a 80p6s-a 80p6q-a 80d0 80p6n-a 80p6q-a 80d0 49152 (49022) 1024 m a s s p r o d u c t 3 2 k 2 8 k 2 4 k 2 0 k 1 6 k 1 2 k 8 k 4 k 2 5 6 384 512 6 4 07 6 88 9 6 1 0 2 4 1 9 2 m 3 8 2 2 2 m 2 r a m s i z e ( b y t e s ) rom size (bytes) 4 8 k m 3 8 2 2 7 e c m a s s p r o d u c t m 3 8 2 2 3 m 4 / e 4 under development
8 single-chip 8-bit cmos microcomputer 3822 group mitsubishi microcomputers group expansion (extended operating temperature version) mitsubishi plans to expand the 3822 group (extended operating temperature version) as follows: memory type support for mask rom version. memory size rom size ........................................................................ 48 k bytes ram size ....................................................................... 1024 bytes package 80p6n-a .................................... 0.8 mm-pitch plastic molded qfp currently products are listed below. memory expansion plan remarks package product as of feb. 2002 ram size (bytes) 49152(49022) rom size (bytes) rom size for user in ( ) fig. 6 memory expansion plan for extended operating temperature version table 4 list of products for extended operating temperature version m38227mcdxxxfp 1024 80p6n-a mask rom version 3 2 k 2 8 k 2 4 k 2 0 k 1 6 k 1 2 k 8 k 4 k 2 5 6 384 512 6 4 07 6 88 9 6 1 0 2 4 1 9 2 r a m s i z e ( b y t e s ) rom size (bytes) 4 8 k m a s s p r o d u c t m 3 8 2 2 7 m c d
9 single-chip 8-bit cmos microcomputer 3822 group mitsubishi microcomputers group expansion (m version) mitsubishi plans to expand the 3822 group (m version) as follows: memory type support for mask rom version. memory size rom size ........................................................... 16 k to 24 k bytes ram size .............................................................. 512 to 640 bytes package 80p6n-a .................................... 0.8 mm-pitch plastic molded qfp 80p6s-a .................................. 0.65 mm-pitch plastic molded qfp 80p6q-a .................................... 0.5 mm-pitch plastic molded qfp currently products are listed below. memory expansion plan remarks package product as of feb. 2002 ram size (bytes) 16384 (16254) rom size (bytes) rom size for user in ( ) 24576 (24446) fig. 7 memory expansion plan for m version table 5 list of products for m version m38223m4mxxxfp m38223m4mxxxgp m38223m4mxxxhp m38224m6mxxxfp m38224m6mxxxhp 512 640 80p6n-a 80p6s-a 80p6q-a 80p6n-a 80p6q-a mask rom version mask rom version mask rom version mask rom version mask rom version m a s s p r o d u c t 3 2 k 2 8 k 2 4 k 2 0 k 1 6 k 1 2 k 8 k 4 k 2 5 63 8 45 1 26 4 07 6 88 9 6 1 0 2 4 1 9 2 m 3 8 2 2 4 m 6 m r a m s i z e ( b y t e s ) r o m s i z e ( b y t e s ) 4 8 k m a s s p r o d u c t m 3 8 2 2 3 m 4 m
10 single-chip 8-bit cmos microcomputer 3822 group mitsubishi microcomputers group expansion (h version) mitsubishi plans to expand the 3822 group (h version) as follows: memory type support for mask rom version. memory size rom size ........................................................... 16 k to 48 k bytes ram size ............................................................ 512 to 1024 bytes package 80p6n-a .................................... 0.8 mm-pitch plastic molded qfp 80p6q-a .................................... 0.5 mm-pitch plastic molded qfp currently products are listed below. memory expansion plan remarks package product as of feb. 2002 ram size (bytes) 16384 (16254) rom size (bytes) rom size for user in ( ) 24576 (24446) fig. 8 memory expansion plan for h version table 6 list of products for h version m38223m4hxxxfp m38223m4hxxxhp m38224m6hxxxfp m38224m6hxxxhp m38227m8hxxxfp m38227m8hxxxhp m38227mchxxxfp m38227mchxxxhp 512 80p6n-a 80p6q-a 80p6n-a 80p6q-a 80p6n-a 80p6q-a 80p6n-a 80p6q-a mask rom version mask rom version mask rom version mask rom version mask rom version mask rom version mask rom version mask rom version 640 32768 (32638) 49152 (49022) 1024 mass product mass product 3 2 k 28k 2 4 k 2 0 k 16k 1 2 k 8 k 4 k 2 5 63 8 45 1 2 640 768 8 9 6 1024 192 m38223m4h ram size (bytes) r o m s i z e ( b y t e s ) 4 8 k mass product m38224m6h m 3 8 2 2 7 m 8 h mass product m 3 8 2 2 7 m c h
11 single-chip 8-bit cmos microcomputer 3822 group mitsubishi microcomputers functional description central processing unit (cpu) the 3822 group uses the standard 740 family instruction set. re- fer to the table of 740 family addressing modes and machine instructions or the 740 family software manual for details on the instruction set. machine-resident 740 family instructions are as follows: the fst and slw instruction cannot be used. the stp, wit, mul, and div instruction can be used. [accumulator (a)] the accumulator is an 8-bit register. data operations such as data transfer, etc., are executed mainly through the accumulator. [index register x (x)] the index register x is an 8-bit register. in the index addressing modes, the value of the operand is added to the contents of register x and specifies the real address. [index register y (y)] the index register y is an 8-bit register. in partial instruction, the value of the operand is added to the contents of register y and specifies the real address. [stack pointer (s)] the stack pointer is an 8-bit register used during subroutine calls and interrupts. this register indicates start address of stored area (stack) for storing registers during subroutine calls and interrupts. the low-order 8 bits of the stack address are determined by the contents of the stack pointer. the high-order 8 bits of the stack ad- dress are determined by the stack page selection bit. if the stack page selection bit is 0 , the high-order 8 bits becomes 00 16 . if the stack page selection bit is 1 , the high-order 8 bits becomes 01 16 . the operations of pushing register contents onto the stack and popping them from the stack are shown in figure 10. store registers other than those described in figure 10 with pro- gram when the user needs them during interrupts or subroutine calls. [program counter (pc)] the program counter is a 16-bit counter consisting of two 8-bit registers pc h and pc l . it is used to indicate the address of the next instruction to be executed. fig.9 740 family cpu register structure a accumulator b7 b7 b7 b7 b0 b7 b15 b0 b7 b0 b0 b0 b0 x index register x y index register y s stack pointer pc l program counter pc h n v t b d i z c processor status register (ps) carry flag zero flag interrupt disable flag decimal mode flag break flag index x mode flag overflow flag negative flag
12 single-chip 8-bit cmos microcomputer 3822 group mitsubishi microcomputers table 7 push and pop instructions of accumulator or processor status register accumulator processor status register push instruction to stack pha php pop instruction from stack pla plp fig. 10 register push and pop at interrupt generation and subroutine call note : condition for acceptance of an interrupt interrupt enable flag is 1 e x e c u t e j s r o n - g o i n g r o u t i n e m ( s )( p c h ) ( s ) ( s ) C 1 m ( s )( p c l ) e x e c u t e r t s ( p c l )m ( s ) (s) (s) C 1 ( s ) ( s ) + 1 (s) (s) + 1 ( p c h )m ( s ) subroutine pop return address from stack p u s h r e t u r n a d d r e s s o n s t a c k m ( s )( p s ) execute rti (ps) m (s) ( s ) ( s ) C 1 ( s ) ( s ) + 1 interrupt service routine pop contents of processor status register from stack m (s) (pc h ) ( s ) ( s ) C 1 m ( s )( p c l ) ( s ) ( s ) C 1 (pc l )m (s) ( s ) ( s ) + 1 ( s ) ( s ) + 1 (pc h )m (s) pop return address from stack i flag is set from 0 to 1 fetch the jump vector push return address on stack push contents of processor status register on stack interrupt request (note) i n t e r r u p t d i s a b l e f l a g i s 0
13 single-chip 8-bit cmos microcomputer 3822 group mitsubishi microcomputers [processor status register (ps)] the processor status register is an 8-bit register consisting of 5 flags which indicate the status of the processor after an arithmetic operation and 3 flags which decide mcu operation. branch opera- tions can be performed by testing the carry (c) flag , zero (z) flag, overflow (v) flag, or the negative (n) flag. in decimal mode, the z, v, n flags are not valid. ?bit 0: carry flag (c) the c flag contains a carry or borrow generated by the arithmetic logic unit (alu) immediately after an arithmetic operation. it can also be changed by a shift or rotate instruction. ?bit 1: zero flag (z) the z flag is set if the result of an immediate arithmetic operation or a data transfer is 0, and cleared if the result is anything other than 0. ?bit 2: interrupt disable flag (i) the i flag disables all interrupts except for the interrupt generated by the brk instruction. interrupts are disabled when the i flag is 1. ?bit 3: decimal mode flag (d) the d flag determines whether additions and subtractions are executed in binary or decimal. binary arithmetic is executed when this flag is 0; decimal arithmetic is executed when it is 1. decimal correction is automatic in decimal mode. only the adc and sbc instructions can be used for decimal arithmetic. ?bit 4: break flag (b) the b flag is used to indicate that the current interrupt was generated by the brk instruction. the brk flag in the processor status register is always 0. when the brk instruction is used to generate an interrupt, the processor status register is pushed onto the stack with the break flag set to 1. ?bit 5: index x mode flag (t) when the t flag is 0, arithmetic operations are performed between accumulator and memory. when the t flag is 1, direct arithmetic operations and direct data transfers are enabled between memory locations. ?bit 6: overflow flag (v) the v flag is used during the addition or subtraction of one byte of signed data. it is set if the result exceeds +127 to -128. when the bit instruction is executed, bit 6 of the memory location operated on by the bit instruction is stored in the overflow flag. ?bit 7: negative flag (n) the n flag is set if the result of an arithmetic operation or data transfer is negative. when the bit instruction is executed, bit 7 of the memory location operated on by the bit instruction is stored in the negative flag. table 8 set and clear instructions of each bit of processor status register set instruction clear instruction c flag sec clc z flag C C i flag sei cli d flag sed cld b flag C C t flag set clt v flag C clv n flag C C
14 single-chip 8-bit cmos microcomputer 3822 group mitsubishi microcomputers [cpu mode register (cpum)] 003b 16 the cpu mode register contains the stack page selection bit and the internal system clock selection bit. the cpu mode register is allocated at address 003b 16 . fig. 11 structure of cpu mode register not available processor mode bits b1 b0 0 0 : single-chip mode 0 1 : 1 0 : 1 1 : stack page selection bit 0 : 0 page 1 : 1 page not used (returns 1 when read) (do not write 0 to this bit) port x c switch bit 0 : i/o port function (stop oscillating) 1 : x cin C x cout oscillating function main clock (x in C x out ) stop bit 0 : oscillating 1 : stopped main clock division ratio selection bit 0 : f(x in )/2 (high-speed mode) 1 : f(x in )/8 (middle-speed mode) internal system clock selection bit 0 : x in C x out selected (middle-/high-speed mode) 1 : x cin C x cout selected (low-speed mode) cpu mode register (cpum (cm) : address 003b 16 ) b7 b0
15 single-chip 8-bit cmos microcomputer 3822 group mitsubishi microcomputers memory special function register (sfr) area the special function register area in the zero page contains con- trol registers such as i/o ports and timers. ram ram is used for data storage and for stack area of subroutine calls and interrupts. rom the first 128 bytes and the last 2 bytes of rom are reserved for device testing and the rest is user area for storing programs. interrupt vector area the interrupt vector area contains reset and interrupt vectors. zero page the 256 bytes from addresses 0000 16 to 00ff 16 are called the zero page area. the internal ram and the special function regis- ter (sfr) are allocated to this area. the zero page addressing mode can be used to specify memory and register addresses in the zero page area. access to this area with only 2 bytes is possible in the zero page addressing mode. special page the 256 bytes from addresses ff00 16 to ffff 16 are called the special page area. the special page addressing mode can be used to specify memory addresses in the special page area. access to this area with only 2 bytes is possible in the special page addressing mode. fig. 12 memory map diagram 1 9 2 2 5 6 3 8 4 5 1 2 6 4 0 7 6 8 8 9 6 1 0 2 4 0 0 f f 1 6 0 1 3 f 1 6 0 1 b f 1 6 0 2 3 f 1 6 0 2 b f 1 6 0 3 3 f 1 6 0 3 b f 1 6 0 4 3 f 1 6 r a m a r e a r a m s i z e ( b y t e s ) a d d r e s s x x x x 1 6 4 0 9 6 8 1 9 2 1 2 2 8 8 1 6 3 8 4 2 0 4 8 0 2 4 5 7 6 2 8 6 7 2 3 2 7 6 8 3 6 8 6 4 4 0 9 6 0 4 5 0 5 6 4 9 1 5 2 f 000 16 e000 16 d000 16 c000 16 b000 16 a000 16 9000 16 8000 16 7000 16 6000 16 5000 16 4000 16 f 080 16 e080 16 d080 16 c080 16 b080 16 a080 16 9080 16 8080 16 7080 16 6080 16 5080 16 4080 16 r o m a r e a rom s i ze (bytes) a d d r e s s y y y y 1 6 a d d r e s s z z z z 1 6 0100 16 0 0 0 0 1 6 0 0 4 0 1 6 0 8 4 0 1 6 f f 0 0 1 6 ffdc 16 fffe 16 f f f f 1 6 x x x x 1 6 y y y y 1 6 zzzz 16 ram rom r eserve d area sfr area n ot use d i n t e r r u p t v e c t o r a r e a r eserve d rom area (128 bytes) z ero page s pec i a l page r eserve d rom area 0 0 5 0 1 6 l c d d i s p l a y r a m a r e a
16 single-chip 8-bit cmos microcomputer 3822 group mitsubishi microcomputers fig. 13 memory map of special function register (sfr) 0020 16 0021 16 0022 16 0023 16 0024 16 0025 16 0026 16 0027 16 0028 16 0029 16 002a 16 002b 16 002c 16 002d 16 002e 16 002f 16 0030 16 0031 16 0032 16 0033 16 0034 16 0035 16 0036 16 0037 16 0038 16 0039 16 003a 16 003b 16 003c 16 003d 16 003e 16 003f 16 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 0010 16 0011 16 0012 16 0013 16 0014 16 0015 16 0016 16 0017 16 0018 16 0019 16 001a 16 001b 16 001c 16 001d 16 001e 16 001f 16 port p0 (p0) port p1 (p1) port p1 output control register (p1d) port p2 (p2) port p2 direction register (p2d) port p3 (p3) port p4 (p4) port p4 direction register (p4d) port p5 (p5) port p5 direction register (p5d) port p6 (p6) port p6 direction register (p6d) port p7 (p7) port p7 direction register (p7d) serial i/o status register (siosts) serial i/o control register (sio1con) uart control register (uartcon) baud rate generator (brg) interrupt control register 2(icon2) timer 3 (t3) timer x mode register (txm) interrupt edge selection register (intedge) cpu mode register (cpum) interrupt request register 1(ireq1) interrupt request register 2(ireq2) interrupt control register 1(icon1) timer x (low) (txl) timer y (low) (tyl) timer 1 (t1) timer 2 (t2) timer x (high) (txh) timer y (high) (tyh) pull register a (pulla) pull register b (pullb) timer y mode register (tym) timer 123 mode register (t123m) output control register (ckout) segment output enable register (seg) lcd mode register (lm) a-d control register (adcon) a-d conversion register (ad) transmit/receive buffer register (tb/rb) port p0 direction register (p0d)
17 single-chip 8-bit cmos microcomputer 3822 group mitsubishi microcomputers i/o ports direction registers (ports p2, p4 1 -p4 7 , and p5-p7) the 3822 group has 49 programmable i/o pins arranged in seven i/o ports (ports p0 C p2, p4 1 C p4 7 and p5-p7). the i/o ports p2, p4 1 C p4 7 and p5-p7 have direction registers which determine the input/output direction of each individual pin. each bit in a direction register corresponds to one pin, and each pin can be set to be in- put port or output port. when 0 is written to the bit corresponding to a pin, that pin be- comes an input pin. when 1 is written to that bit, that pin be- comes an output pin. if data is read from a pin set to output, the value of the port output latch is read, not the value of the pin itself. pins set to input are floating. if a pin set to input is written to, only the port output latch is written to and the pin remains floating. direction registers (ports p0 and p1) ports p0 and p1 have direction registers which determine the in- put/output direction of each individual port. each port in a direction register corresponds to one port, each port can be set to be input or output. when 0 is written to the bit 0 of a direction register, that port becomes an input port. when 1 is written to that port, that port becomes an output port. bits 1 to 7 of ports p0 and p1 direction registers are not used. ports p3 and p4 0 these ports are only for input. pull-up/pull-down control by setting the pull register a (address 0016 16 ) or the pull reg- ister b (address 0017 16 ), ports except for port p4 0 can control either pull-down or pull-up (pins that are shared with the segment output pins for lcd are pull-down; all other pins are pull-up) with a program. however, the contents of pull register a and pull register b do not affect ports programmed as the output ports. fig. 14 structure of pull register a and pull register b p 0 0 C p 0 7 pu ll - d own p1 0 C p1 7 pull-down p2 0 C p2 7 pull-up p3 4 C p3 7 pull-down p7 0 , p7 1 pull-up not used (return 0 when read) p u l l r e g i s t e r a ( p u l l a : a d d r e s s 0 0 1 6 1 6 ) b 7 b 0 p 4 1 C p 4 3 pu ll -up p4 4 C p4 7 pull-up p5 0 C p5 3 pull-up p5 4 C p5 7 pull-up p6 0 C p6 3 pull-up p6 4 C p6 7 pull-up not used (return 0 when read) 0 : d i s a b l e 1 : e n a b l e p u l l r e g i s t e r b ( p u l l b : a d d r e s s 0 0 1 7 1 6 ) b 7 b 0 n ote : th e contents o f pull reg i ster a an d pull reg i ster b do not affect ports programmed as the output port.
18 single-chip 8-bit cmos microcomputer 3822 group mitsubishi microcomputers real time port function output a-d conversion input a-d trigger input diagram no. related sfrs input/output name pin non-port function i/o format table 9 list of i/o port function p0 0 /seg 16 C p0 7 /seg 23 p1 0 /seg 24 C p1 7 /seg 31 p2 0 C p2 7 p3 4 /seg 12 C p3 7 /seg 15 p4 0 p4 1 / p4 2 /int 0, p4 3 /int 1 p4 4 /r x d p4 5 /t x d p4 6 /s clk p4 7 /s rdy p5 0 /int 2 , p5 1 /int 3 p5 2 /rtp 0 , p5 3 /rtp 1 p5 4 /cntr 0 port p0 port p1 port p2 port p3 port p4 input/output, individual ports input/output, individual bits input input input/output, individual bits cmos compatible input level cmos 3-state output cmos compatible input level cmos 3-state output cmos compatible input level cmos compatible input level cmos compatible input level cmos 3-state output cmos compatible input level cmos 3-state output cmos compatible input level cmos 3-state output cmos compatible input level cmos 3-state output lcd segment output key input (key-on wake-up) interrupt input lcd segment output clock output external interrupt input serial i/o function i/o external interrupt input timer x function i/o timer y function input timer 2 function output pull register a segment output enable register pull register a interrupt control register 2 pull register a segment output enable register pull register b output control register pull register b interrupt edge selection register pull register b serial i/o control register serial i/o status register uart control register pull register b interrupt edge selection register pull register b timer x mode register pull register b timer x mode register pull register b timer y mode register pull register b timer 123 mode register pull register b a-d control register pull register a cpu mode register (1) (2) (3) (4) (6) (5) (2) (8) (7) port p5 (9) (2) input/output, individual bits (10) p5 5 /cntr 1 (11) (12) (13) (12) (14) p5 6 /t out p5 7 /adt p6 0 /an 0 C p6 7 /an 7 (15) p7 0 /x cout p7 1 /x cin com 0 C com 3 seg 0 C seg 11 (16) (17) (18) input/output, individual bits input/output, individual bits output output sub-clock generating circuit i/o lcd common output lcd segment output notes1: how to use double-function ports as function i/o ports, refer to the applicable sections. 2: make sure that the input level at each pin is either 0 v or v cc during execution of the stp instruction. when an input level is at an intermediate po- tential, a current will flow v cc to v ss through the input-stage gate. port p6 port p7 common segment lcd mode register
19 single-chip 8-bit cmos microcomputer 3822 group mitsubishi microcomputers fig. 15 port block diagram (1) (3) ports p3 4 C p3 7 v l2 /v l3 v l1 /v ss (1) ports p0, p1 segment output enable bit v l2 /v l3 v l1 /v ss (note) (2) ports p2, p4 2 , p4 3 , p5 0 , p5 1 direction register (5) port p4 1 direction register (6) port p4 4 receive enable bit direction register (4) port p4 0 data bus pull-down control segment output enable bit data bus direction register port latch pull-down control segment output enable bit note: bit 0 of direction register. data bus port latch pull-up control key input (key-on wake-up) interrupt input int 0 C int 3 interrupt input output control bit pull-up control data bus port latch pull-up control serial i/o enable bit serial i/o input data bus port latch data bus
20 single-chip 8-bit cmos microcomputer 3822 group mitsubishi microcomputers fig. 16 port block diagram (2) direction register port latch serial i/o enable bit transmit enable bit p4 5 /t x d p-channel output disable bit pull-up control (7) port p4 5 serial i/o output data bus direction register port latch data bus serial i/o ready output serial i/o mode selection bit pull-up control (9) port p4 7 (8) port p4 6 serial i/o clock- synchronized selection bit serial i/o enable bit serial i/o mode selection bit serial i/o enable bit direction register port latch serial i/o clock output data bus serial i/o clock input pull-up control (10) ports p5 2, p5 3 direction register port latch data bus pull-up control real time port control bit data for real time port direction register port latch data bus pull-up control (12) ports p5 5, p5 7 cntr 1 interrupt input a-d trigger interrupt input (11) port p5 4 direction register port latch data bus pull-up control timer x operating mode bit timer output cntr 0 interrupt input serial i/o enable bit s rdy output enable bit (pulse output mode selection)
21 single-chip 8-bit cmos microcomputer 3822 group mitsubishi microcomputers fig. 17 port block diagram (3) v l2 /v l3 v l 1 / v s s ( 1 3 ) p o r t p 5 6 d a t a b u s d i r e c t i o n r e g i s t e r p o r t l a t c h p u l - u p c o n t r o l t o u t o u t p u t c o n t r o l b i t t i m e r o u t p u t ( 1 4 ) p o r t p 6 d a t a b u s d i r e c t i o n r e g i s t e r p o r t l a t c h pull-up control a-d conversion input a n a l o g i n p u t p i n s e l e c t i o n b i t ( 1 5 ) p o r t p 7 0 d a t a b u s d i r e c t i o n r e g i s t e r p o r t l a t c h p o r t x c s w i t c h b i t + p u l l - u p c o n t r o l port x c switch bit oscillation circuit p o r t p 7 1 p o r t x c s w i t c h b i t ( 1 6 ) p o r t p 7 1 data bus d i r e c t i o n r e g i s t e r p o r t l a t c h port x c switch bit p o r t x c s w i t c h b i t + p u l l - u p c o n t r o l sub-clock generating circuit input v l3 v l2 v l1 ( 1 7 ) c o m 0 C c o m 3 ( 1 8 ) s e g 0 C s e g 1 1 t h e g a t e i n p u t s i g n a l o f e a c h t r a n s i s t o r i s c o n t r o l l e d b y t h e l c d d u t y r a t i o a n d t h e b i a s v a l u e . the voltage applied to the sources of p-channel and n-channel transistors is the controlled voltage by the bias value.
22 single-chip 8-bit cmos microcomputer 3822 group mitsubishi microcomputers interrupts interrupts occur by seventeen sources: eight external, eight inter- nal, and one software. interrupt control each interrupt is controlled by an interrupt request bit, an interrupt enable bit, and the interrupt disable flag except for the software interrupt set by the brk instruction. an interrupt occurs if the cor- responding interrupt request and enable bits are 1 and the interrupt disable flag is 0. interrupt enable bits can be set or cleared by software. interrupt request bits can be cleared by software, but cannot be set by software. the brk instruction cannot be disabled with any flag or bit. the i flag disables all interrupts except the brk instruction interrupt. when several interrupts occur at the same time, the interrupts are received according to priority. interrupt operation upon acceptance of an interrupt the following operations are auto- matically performed: 1. the contents of the program counter and processor status register are automatically pushed onto the stack. 2. the interrupt disable flag is set and the corresponding interrupt request bit is cleared. 3. the interrupt jump destination address is read from the vec- tor table into the program counter. notes on interrupts when setting the followings, the interrupt request bit may be set to 1. ?when setting external interrupt active edge related register: interrupt edge selection register (address 3a 16 ) timer x mode register (address 27 16 ) timer y mode register (address 28 16 ) ?when switching interrupt sources of an interrupt vector address where two or more interrupt sources are allocated related register: a-d control regsiter (address 34 16 ) when not requiring for the interrupt occurrence synchronized with these setting, take the following sequence. ? set the corresponding interrupt enable bit to 0 (disabled). ? set the interrupt edge select bit or the interrupt source select bit to 1. ? set the corresponding interrupt request bit to 0 after 1 or more instructions have been executed. ? set the corresponding interrupt enable bit to 1 (enabled). notes1: vector addresses contain interrupt jump destination addresses. 2: reset function in the same way as an interrupt with the highest priority. table 10 interrupt vector addresses and priority remarks interrupt request generating conditions at reset at detection of either rising or falling edge of int 0 input at detection of either rising or falling edge of int 1 input at completion of serial i/o data reception at completion of serial i/o trans- mit shift or when transmission buffer is empty interrupt source low high priority vector addresses (note 1) reset (note 2) int 0 int 1 serial i/o reception serial i/o transmission timer x timer y timer 2 timer 3 cntr 0 cntr 1 timer 1 int 2 int 3 key input (key-on wake-up) adt a-d conversion brk instruction 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 fffd 16 fffb 16 fff9 16 fff7 16 fff5 16 fff3 16 fff1 16 ffef 16 ffed 16 ffeb 16 ffe9 16 ffe7 16 ffe5 16 ffe3 16 ffe1 16 ffdf 16 ffdd 16 fffc 16 fffa 16 fff8 16 fff6 16 fff4 16 fff2 16 fff0 16 ffee 16 ffec 16 ffea 16 ffe8 16 ffe6 16 ffe4 16 ffe2 16 ffe0 16 ffde 16 ffdc 16 at timer x underflow at timer y underflow at timer 2 underflow at timer 3 underflow at detection of either rising or falling edge of cntr 0 input at detection of either rising or falling edge of cntr 1 input at timer 1 underflow at detection of either rising or falling edge of int 2 input at detection of either rising or falling edge of int 3 input at falling of conjunction of input level for port p2 (at input mode) at falling of adt input at completion of a-d conversion at brk instruction execution non-maskable external interrupt (active edge selectable) external interrupt (active edge selectable) valid when serial i/o is selected valid when serial i/o is selected external interrupt (active edge selectable) external interrupt (active edge selectable) external interrupt (active edge selectable) external interrupt (active edge selectable) external interrupt (valid at falling) valid when adt interrupt is se- lected, external interrupt (valid at falling) valid when a-d interrupt is se- lected non-maskable software interrupt
23 single-chip 8-bit cmos microcomputer 3822 group mitsubishi microcomputers fig. 18 interrupt control fig. 19 structure of interrupt-related registers interrupt request bit interrupt enable bit interrupt disable flag (i) brk instruction reset interrupt request b7 b0 interrupt edge selection register int 0 interrupt edge selection bit int 1 interrupt edge selection bit int 2 interrupt edge selection bit int 3 interrupt edge selection bit not used (return 0 when read) (intedge : address 003a 16 ) interrupt request register 1 int 0 interrupt request bit int 1 interrupt request bit serial i/o receive interrupt request bit serial i/o transmit interrupt request bit timer x interrupt request bit timer y interrupt request bit timer 2 interrupt request bit timer 3 interrupt request bit interrupt control register 1 int 0 interrupt enable bit int 1 interrupt enable bit serial i/o receive interrupt enable bit serial i/o transmit interrupt enable bit timer x interrupt enable bit timer y interrupt enable bit timer 2 interrupt enable bit timer 3 interrupt enable bit 0 : no interrupt request issued 1 : interrupt request issued (ireq1 : address 003c 16 ) (icon1 : address 003e 16 ) interrupt request register 2 cntr 0 interrupt request bit cntr 1 interrupt request bit timer 1 interrupt request bit int 2 interrupt request bit int 3 interrupt request bit key input interrupt request bit adt/ad conversion interrupt request bit not used (returns 0 when read) (ireq2 : address 003d 16 ) interrupt control register 2 cntr 0 interrupt enable bit cntr 1 interrupt enable bit timer 1 interrupt enable bit int 2 interrupt enable bit int 3 interrupt enable bit key input interrupt enable bit adt/ad conversion interrupt enable bit not used (returns 0 when read) (do not write 1 to this bit.) 0 : interrupts disabled 1 : interrupts enabled (icon2 : address 003f 16 ) 0 : falling edge active 1 : rising edge active b7 b0 b7 b0 b7 b0 b7 b0
24 single-chip 8-bit cmos microcomputer 3822 group mitsubishi microcomputers key input interrupt (key-on wake-up) a key-on wake-up interrupt request is generated by applying a falling edge to any pin of port p2 that have been set to input mode. in other words, it is generated when and of input level goes from 1 to 0 . an example of using a key input interrupt is shown in figure 20, where an interrupt request is generated by pressing one of the keys consisted as an active-low key matrix which inputs to ports p2 0 C p2 3 . fig. 20 connection example when using key input interrupt and port p2 block diagram p o r t p x x l l e v e l o u t p u t port p2 7 direction register = 1 p 2 7 o u t p u t p2 6 output pull register a bit 2 = 1 p 2 5 o u t p u t p 2 4 o u t p u t p 2 3 i n p u t p o r t p 2 6 l a t c h p o r t p 2 5 l a t c h p o r t p 2 4 l a t c h port p2 3 latch p o r t p 2 7 l a t c h p o r t p 2 5 d i r e c t i o n r e g i s t e r = 1 port p2 4 direction register = 1 port p2 3 direction register = 0 p2 2 input p 2 1 i n p u t p 2 0 i n p u t p o r t p 2 2 l a t c h p o r t p 2 1 l a t c h port p2 0 latch p o r t p 2 2 d i r e c t i o n r e g i s t e r = 0 p o r t p 2 1 d i r e c t i o n r e g i s t e r = 0 port p2 0 direction register = 0 p o r t p 2 i n p u t r e a d i n g c i r c u i t ? p - c h a n n e l t r a n s i s t o r f o r p u l l - u p ? ? c m o s o u t p u t b u f f e r k e y i n p u t i n t e r r u p t r e q u e s t p o r t p 2 6 d i r e c t i o n r e g i s t e r = 1 ? ? ? ?? ? ?? ? ?? ? ?? ? ?? ? ?? ? ??
25 single-chip 8-bit cmos microcomputer 3822 group mitsubishi microcomputers timers the 3822 group has five timers: timer x, timer y, timer 1, timer 2, and timer 3. timer x and timer y are 16-bit timers, and timer 1, timer 2, and timer 3 are 8-bit timers. all timers are down count timers. when the timer reaches 00 16 , an underflow occurs at the next count pulse and the correspond- ing timer latch is reloaded into the timer and the count is continued. when a timer underflows, the interrupt request bit cor- responding to that timer is set to 1. read and write operation on 16-bit timer must be performed for both high and low-order bytes. when reading a 16-bit timer, read the high-order byte first. when writing to a 16-bit timer, write the low-order byte first. the 16-bit timer cannot perform the correct operation when reading during the write operation, or when writing during the read operation. fig. 21 timer block diagram cntr 0 act i ve edge switch bit ti mer 1 count source selection bit r ea l t i me port control bit 0 1 p 5 5 / c n t r 1 0 f(x in )/16 ( f ( x cin ) 516 in low-s p eed mode ? 1 0 t i m e r y s t o p c o n t r o l b i t falling edge detection p er i o d measurement mode ti mer y interrupt request pulse width hl continuously measurement mode r i s i n g e d g e d e t e c t i o n 0 0 , 0 1 , 1 1 ti mer y operat i ng mode bits ti mer x interrupt request ti mer x mo d e reg i ster write signal p 5 4 / c n t r 0 q q t s p 5 4 d i r e c t i o n r e g i s t e r p u l s e o u t p u t m o d e p 5 4 l a t c h ti mer x stop control bit 0 1 ti mer x wr i te control bit q d l a t c h q d l a t c h 1 0 1 1 0 timer x operat- ing mode bits 00 , 01 , 11 f ( x i n ) / 1 6 ( f ( x i n ) / 1 6 i n l o w - s p e e d m o d e ? 0 p 5 6 di rect i on reg i ster p 5 6 l atc h 1 t o u t o u t p u t a c t i v e e d g e s w i t c h b i t ti mer 2 wr i te control bit 0 1 t o u t o u t p u t c o n t r o l b i t 1 p 5 6 / t out x cin t i m e r 3 c o u n t s o u r c e s e l e c t i o n b i t 0 1 t i m e r 2 i n t e r r u p t r e q u e s t ti mer 3 interrupt request ti mer 2 count source selection bit ti mer 1 interrupt request d a t a b u s f(x in ) /16 ( f ( x cin ) /16 in low-s p eed mode ] ) f ( x i n ) / 1 6 ( f ( x c i n ) / 1 6 i n l o w - s p e e d m o d e ? ? 0 0 , 0 1 , 1 0 1 1 r e a l t i m e p o r t c o n t r o l b i t 1 p 5 2 l a t c h r e a l t i m e p o r t c o n t r o l b i t 1 p 5 3 l a t c h timer y (low) (8) t i m e r y ( h i g h ) ( 8 ) ti mer 3 l atc h ( 8 ) ti mer 3 ( 8 ) t i m e r 1 l a t c h ( 8 ) t i m e r 1 ( 8 ) t i m e r 2 l a t c h ( 8 ) ti mer 2 ( 8 ) timer x (low) (8) timer x (high) (8) t i m e r x ( l o w ) l a t c h ( 8 ) timer x (high) latch (8) t i m e r y ( l o w ) l a t c h ( 8 ) timer y (high) latch (8) t out output control bit 0 0 0 p 5 2 p 5 3 p 5 2 d i r e c t i o n r e g i s t e r p 5 3 di rect i on reg i ster p 5 2 d a t a f o r r e a l t i m e p o r t p 5 3 d a t a f o r r e a l t i m e p o r t ?
26 single-chip 8-bit cmos microcomputer 3822 group mitsubishi microcomputers timer x timer x is a 16-bit timer that can be selected in one of four modes and can be controlled the timer x write and the real time port by setting the timer x mode register. (1) timer mode the timer counts f(x in )/16 (or f(x cin )/16 in low-speed mode). (2) pulse output mode each time the timer underflows, a signal output from the cntr 0 pin is inverted. except for this, the operation in pulse output mode is the same as in timer mode. when using a timer in this mode, set the corresponding port p5 4 direction register to output mode. (3) event counter mode the timer counts signals input through the cntr 0 pin. except for this, the operation in event counter mode is the same as in timer mode. when using a timer in this mode, set the corre- sponding port p5 4 direction register to input mode. (4) pulse width measurement mode the count source is f(x in )/16 (or f(x cin )/16 in low-speed mode). if cntr 0 active edge switch bit is 0 , the timer counts while the in- put signal of cntr 0 pin is at h . if it is 1 , the timer counts while the input signal of cntr 0 pin is at l . when using a timer in this mode, set the corresponding port p5 4 direction register to input mode. timer x write control if the timer x write control bit is 0 , when the value is written in the address of timer x, the value is loaded in the timer x and the latch at the same time. if the timer x write control bit is 1 , when the value is written in the address of timer x, the value is loaded only in the latch. the value in the latch is loaded in timer x after timer x underflows. if the value is written in latch only, when writing in the timer latch at the timer underflow, the value is set in the timer and the latch at one time. additionally, unexpected value may be set in the high-or- der counter when the writing in high-order latch and the underflow of timer x are performed at the same timing. real time port control while the real time port function is valid, data for the real time port are output from ports p5 2 and p5 3 each time the timer x underflows. (however, after rewriting a data for real time port, if the real time port control bit is changed from 0 to 1 , data are output independent of the timer x operation.) if the data for the real time port is changed while the real time port function is valid, the changed data are output at the next underflow of timer x. before using this function, set the corresponding port direction registers to output mode. note on cntr 0 interrupt active edge selection cntr 0 interrupt active edge depends on the cntr 0 active edge switch bit. fig. 22 structure of timer x mode register t i m e r x m o d e r e g i s t e r ( t x m : a d d r e s s 0 0 2 7 1 6 ) t i m e r x w r i t e c o n t r o l b i t 0 : w r i t e v a l u e i n l a t c h a n d c o u n t e r 1 : w r i t e v a l u e i n l a t c h o n l y r e a l t i m e p o r t c o n t r o l b i t 0 : r e a l t i m e p o r t f u n c t i o n i n v a l i d 1 : r e a l t i m e p o r t f u n c t i o n v a l i d p 5 2 d a t a f o r r e a l t i m e p o r t p 5 3 d a t a f o r r e a l t i m e p o r t t i m e r x o p e r a t i n g m o d e b i t s b 5 b 4 0 0 : t i m e r m o d e 0 1 : p u l s e o u t p u t m o d e 1 0 : e v e n t c o u n t e r m o d e 1 1 : p u l s e w i d t h m e a s u r e m e n t m o d e c n t r 0 a c t i v e e d g e s w i t c h b i t 0 : c o u n t a t r i s i n g e d g e i n e v e n t c o u n t e r m o d e s t a r t f r o m h o u t p u t i n p u l s e o u t p u t m o d e m e a s u r e h p u l s e w i d t h i n p u l s e w i d t h m e a s u r e m e n t m o d e f a l l i n g e d g e a c t i v e f o r c n t r 0 i n t e r r u p t 1 : c o u n t a t f a l l i n g e d g e i n e v e n t c o u n t e r m o d e s t a r t f r o m l o u t p u t i n p u l s e o u t p u t m o d e m e a s u r e l p u l s e w i d t h i n p u l s e w i d t h m e a s u r e m e n t m o d e r i s i n g e d g e a c t i v e f o r c n t r 0 i n t e r r u p t t i m e r x s t o p c o n t r o l b i t 0 : c o u n t s t a r t 1 : c o u n t s t o p b 7 b 0
27 single-chip 8-bit cmos microcomputer 3822 group mitsubishi microcomputers timer y timer y is a 16-bit timer that can be selected in one of four modes. (1) timer mode the timer counts f(x in )/16 (or f(x cin )/16 in low-speed mode). (2) period measurement mode cntr 1 interrupt request is generated at rising/falling edge of cntr 1 pin input signal. simultaneously, the value in timer y latch is reloaded in timer y and timer y continues counting down. ex- cept for the above-mentioned, the operation in period measurement mode is the same as in timer mode. the timer value just before the reloading at rising/falling of cntr 1 pin input signal is retained until the timer y is read once after the reload. the rising/falling timing of cntr 1 pin input signal is found by cntr 1 interrupt. when using a timer in this mode, set the corre- sponding port p5 5 direction register to input mode. (3) event counter mode the timer counts signals input through the cntr 1 pin. except for this, the operation in event counter mode is the same as in timer mode. when using a timer in this mode, set the corre- sponding port p5 5 direction register to input mode. (4) pulse width hl continuously measurement mode cntr 1 interrupt request is generated at both rising and falling edges of cntr 1 pin input signal. except for this, the operation in pulse width hl continuously measurement mode is the same as in period measurement mode. when using a timer in this mode, set the corresponding port p5 5 direction register to input mode. note on cntr 1 interrupt active edge selection cntr 1 interrupt active edge depends on the cntr 1 active edge switch bit. however, in pulse width hl continuously measurement mode, cntr 1 interrupt request is generated at both rising and falling edges of cntr 1 pin input signal regardless of the setting of cntr 1 active edge switch bit. fig. 23 structure of timer y mode register t i m e r y m o d e r e g i s t e r ( t y m : a d d r e s s 0 0 2 8 1 6 ) b 7 b 0 n o t u s e d ( r e t u r n 0 w h e n r e a d ) t i m e r y o p e r a t i n g m o d e b i t s b 5 b 4 0 0 : t i m e r m o d e 0 1 : p e r i o d m e a s u r e m e n t m o d e 1 0 : e v e n t c o u n t e r m o d e 1 1 : p u l s e w i d t h h l c o n t i n u o u s l y m e a s u r e m e n t m o d e c n t r 1 a c t i v e e d g e s w i t c h b i t 0 : c o u n t a t r i s i n g e d g e i n e v e n t c o u n t e r m o d e m e a s u r e t h e f a l l i n g e d g e t o f a l l i n g e d g e p e r i o d i n p e r i o d m e a s u r e m e n t m o d e f a l l i n g e d g e a c t i v e f o r c n t r 1 i n t e r r u p t 1 : c o u n t a t f a l l i n g e d g e i n e v e n t c o u n t e r m o d e m e a s u r e t h e r i s i n g e d g e p e r i o d i n p e r i o d m e a s u r e m e n t m o d e r i s i n g e d g e a c t i v e f o r c n t r 1 i n t e r r u p t t i m e r y s t o p c o n t r o l b i t 0 : c o u n t s t a r t 1 : c o u n t s t o p
28 single-chip 8-bit cmos microcomputer 3822 group mitsubishi microcomputers timer 1, timer 2, timer 3 timer 1, timer 2, and timer 3 are 8-bit timers. the count source for each timer can be selected by timer 123 mode register. the timer latch value is not affected by a change of the count source. how- ever, because changing the count source may cause an inadvertent count down of the timer, rewrite the value of timer whenever the count source is changed. timer 2 write control if the timer 2 write control bit is 0 , when the value is written in the address of timer 2, the value is loaded in the timer 2 and the latch at the same time. if the timer 2 write control bit is 1 , when the value is written in the address of timer 2, the value is loaded only in the latch. the value in the latch is loaded in timer 2 after timer 2 underflows. timer 2 output control when the timer 2 (t out ) is output enabled, an inversion signal from the t out pin is output each time timer 2 underflows. in this case, set the port shared with the t out pin to the output mode. notes on timer 1 to timer 3 when the count source of timer 1 to 3 is changed, the timer count- ing value may be changed large because a thin pulse is generated in count input of timer . if timer 1 output is selected as the count source of timer 2 or timer 3, when timer 1 is written, the counting value of timer 2 or timer 3 may be changed large because a thin pulse is generated in timer 1 output. therefore, set the value of timer in the order of timer 1, timer 2 and timer 3 after the count source selection of timer 1 to 3. fig. 24 structure of timer 123 mode register t out output act i ve e d ge sw i tc h bi t 0 : start at h output 1 : start at l output t out output control bit 0 : t out output disabled 1 : t out output enabled timer 2 write control bit 0 : write data in latch and counter 1 : write data in latch only timer 2 count source selection bit 0 : timer 1 output 1 : f(x in )/16 (or f(x cin )/16 in low-speed mode) timer 3 count source selection bit 0 : timer 1 output 1 : f(x in )/16 (or f(x cin )/16 in low-speed mode) timer 1 count source selection bit 0 : f(x in )/16 (or f(x cin )/16 in low-speed mode) 1 : f(x cin ) not used (return 0 when read) ti mer 123 mo d e reg i ster (t123m :address 0029 16 ) n o t e : i n t e r n a l c l o c k i s f ( x c i n ) / 2 i n t h e l o w - s p e e d m o d e . b 7 b 0
29 single-chip 8-bit cmos microcomputer 3822 group mitsubishi microcomputers serial i/o serial i/o can be used as either clock synchronous or asynchro- nous (uart) serial i/o. a dedicated timer (baud rate generator) is also provided for baud rate generation. (1) clock synchronous serial i/o mode clock synchronous serial i/o can be selected by setting the mode selection bit of the serial i/o control register to 1 . for clock synchronous serial i/o, the transmitter and the receiver must use the same clock. if an internal clock is used, transfer is started by a write signal to the transmit/receive buffer register. fig. 25 block diagram of clock synchronous serial i/o fig. 26 operation of clock synchronous serial i/o function p 4 6 / s c l k p 4 7 / s r d y 1 p 4 4 / r x d p 4 5 / t x d f ( x i n ) 1/4 1 / 4 f / f serial i/o status register s e r i a l i / o c o n t r o l r e g i s t e r r e c e i v e b u f f e r r e g i s t e r a d d r e s s 0 0 1 8 1 6 r e c e i v e s h i f t r e g i s t e r r e c e i v e b u f f e r f u l l f l a g ( r b f ) r e c e i v e i n t e r r u p t r e q u e s t ( r i ) clock control circuit shif t c l oc k s er i a l i / o clock selection bit frequency division ratio 1/(n+1) baud rate generator a d d r e s s 0 0 1 c 1 6 brg count source se l ect i on bi t c l o c k c o n t r o l c i r c u i t falling-edge detector d ata b us a d d r e s s 0 0 1 8 1 6 s h i f t c l o c k t r a n s m i t s h i f t r e g i s t e r s h i f t c o m p l e t i o n f l a g ( t s c ) t ransm i t b u ff er empty fl ag (tbe) t ransm i t i nterrupt request (ti) t ransm i t i nterrupt source se l ect i on bi t a d d r e s s 0 0 1 9 1 6 d a t a b u s a d d r e s s 0 0 1 a 1 6 transmit buffer register t r a n s m i t s h i f t r e g i s t e r (f(x cin ) i n l ow-spee d mo d e ) r e c e i v e e n a b l e s i g n a l s r d y d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 rbf = 1 tsc = 1 t b e = 0 t b e = 1 t s c = 0 t rans f er s hif t c l oc k (1/2 to 1/2048 of the internal clock, or an external clock) s e r i a l o u t p u t t x d s e r i a l i n p u t r x d w r i t e s i g n a l t o r e c e i v e / t r a n s m i t b u f f e r r e g i s t e r ( a d d r e s s 0 0 1 8 1 6 ) o v e r r u n e r r o r ( o e ) d e t e c t i o n n o t e s 1 : t h e t r a n s m i t i n t e r r u p t ( t i ) c a n b e g e n e r a t e d e i t h e r w h e n t h e t r a n s m i t b u f f e r r e g i s t e r h a s e m p t i e d ( t b e = 1 ) o r a f t e r t h e t r a n s m i t s h i f t o p e r a t i o n h a s e n d e d ( t s c = 1 ) , b y s e t t i n g t h e t r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t ( t i c ) o f t h e s e r i a l i / o c o n t r o l r e g i s t e r . 2 : i f d a t a i s w r i t t e n t o t h e t r a n s m i t b u f f e r r e g i s t e r w h e n t s c = 0 , t h e t r a n s m i t c l o c k i s g e n e r a t e d c o n t i n u o u s l y a n d s e r i a l d a t a i s o u t p u t c o n t i n u o u s l y f r o m t h e t x d p i n . 3 : t h e r e c e i v e i n t e r r u p t ( r i ) i s s e t w h e n t h e r e c e i v e b u f f e r f u l l f l a g ( r b f ) b e c o m e s 1 . d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6
30 single-chip 8-bit cmos microcomputer 3822 group mitsubishi microcomputers (2) asynchronous serial i/o (uart) mode clock asynchronous serial i/o mode (uart) can be selected by clearing the serial i/o mode selection bit of the serial i/o control register to 0 . eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. the transmit and receive shift registers each have a buffer regis- ter, but the two buffers have the same address in memory. since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer, and receive data is read from the receive buffer. the transmit buffer can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next character is being received. fig. 27 block diagram of uart serial i/o fig. 28 operation of uart serial i/o function f ( x i n ) 1/4 oe p e f e 1 / 1 6 1/16 d ata b us r e c e i v e b u f f e r r e g i s t e r a d d r e s s 0 0 1 8 1 6 r ece i ve s hif t reg i ster r ece i ve b u ff er f u ll fl ag (rbf) r ece i ve i nterrupt request (ri) b au d rate generato r f r e q u e n c y d i v i s i o n r a t i o 1 / ( n + 1 ) add ress 001 c 16 s t / s p / p a g e n e r a t o r transmit buffer register d a t a b u s t ransm i t s hif t reg i ster a d d r e s s 0 0 1 8 1 6 t ransm i t s hif t reg i ster s hif t comp l et i on fl ag (tsc) t ransm i t b u ff er empty fl ag (tbe) t ransm i t i nterrupt request (ti) add ress 0019 16 s t d e t e c t o r s p d e t e c t o r uart contro l reg i ster add ress 001 b 16 c h a r a c t e r l e n g t h s e l e c t i o n b i t a d d r e s s 0 0 1 a 1 6 brg count source se l ect i on bit t ransm i t i nterrupt source se l ect i on bit s e r i a l i / o s y n c h r o n o u s c l o c k s e l e c t i o n b i t cl oc k contro l c i rcu i t ch aracter l engt h se l ect i on bi t 7 bits 8 b i t s serial i/o control register p 4 6 / s c l k s er i a l i / o status reg i ster p 4 4 / r x d p 4 5 / t x d ( f ( x c i n ) i n l o w - s p e e d m o d e ) t s c = 0 t b e = 1 r b f = 0 t b e = 0 t b e = 0 r b f = 1 rbf =1 st d 0 d 1 s p d 0 d 1 s t sp tbe =1 tsc=1 ? st d 0 d 1 sp d 0 d 1 st sp t ransm i t b u ff er wr i te s i gna l ? generated at 2nd bit in 2-stop-bit mode 1 s t a r t b i t 7 o r 8 d a t a b i t s 1 o r 0 p a r i t y b i t 1 o r 2 s t o p b i t ( s ) 1 : e r r o r f l a g d e t e c t i o n o c c u r s a t t h e s a m e t i m e t h a t t h e r b f f l a g b e c o m e s 1 ( a t 1 s t s t o p b i t , d u r i n g r e c e p t i o n ) . 2 : t h e t r a n s m i t i n t e r r u p t ( t i ) c a n b e s e l e c t e d t o o c c u r w h e n e i t h e r t h e t b e o r t s c f l a g b e c o m e s 1 b y t h e s e t t i n g o f t h e t r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t ( t i c ) o f t h e s e r i a l i / o c o n t r o l r e g i s t e r . 3 : t h e r e c e i v e i n t e r r u p t ( r i ) i s s e t w h e n t h e r b f f l a g b e c o m e s 1 . 4 : a f t e r d a t a i s w r i t t e n t o t h e t r a n s m i t b u f f e r r e g i s t e r w h e n t s c = 1 , 0 . 5 t o 1 . 5 c y c l e s o f t h e d a t a s h i f t c y c l e i s n e c e s s a r y u n t i l c h a n g i n g t o t s c = 0 . n o t e s s e r i a l o u t p u t t x d s e r i a l i n p u t r x d r e c e i v e b u f f e r r e a d s i g n a l t r a n s m i t o r r e c e i v e c l o c k
31 single-chip 8-bit cmos microcomputer 3822 group mitsubishi microcomputers [transmit buffer/receive buffer register (tb/rb)] 0018 16 the transmit buffer register and the receive buffer register are lo- cated at the same address. the transmit buffer register is write-only and the receive buffer register is read-only. if a charac- ter bit length is 7 bits, the msb of data stored in the receive buffer register is 0. [serial i/o status register (siosts)] 0019 16 the read-only serial i/o status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial i/o function and various errors. three of the flags (bits 4 to 6) are valid only in uart mode. the receive buffer full flag (bit 1) is cleared to 0 when the receive buffer is read. if there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer reg- ister, and the receive buffer full flag is set. a write to the serial i/o status register clears all the error flags oe, pe, fe, and se. writ- ing 0 to the serial i/o enable bit (sioe) also clears all the status flags, including the error flags. all bits of the serial i/o status register are initialized to 0 at reset, but if the transmit enable bit (bit 4) of the serial i/o control register has been set to 1, the transmit shift register shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become 1. [serial i/o control register (siocon)] 001a 16 the serial i/o control register contains eight control bits for the se- rial i/o function. [uart control register (uartcon) ]001b 16 the uart control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial i/o is selected and set the data format of an data transfer. one bit in this register (bit 4) is always valid and sets the output structure of the p4 5 /t x d pin. [baud rate generator (brg)] 001c 16 the baud rate generator determines the baud rate for serial trans- fer. the baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate genera- tor. notes on serial i/o when setting the transmit enable bit to 1, the serial i/o transmit interrupt request bit is automatically set to 1. when not requiring the interrupt occurrence synchronized with the transmission enalbed, take the following sequence. ? set the serial i/o transmit interrupt enable bit to 0 (disabled). ? set the transmit enable bit to 1. ? set the serial i/o transmit interrupt request bit to 0 after 1 or more instructions have been executed. ? set the serial i/o transmit interrupt enable bit to 1 (enabled).
32 single-chip 8-bit cmos microcomputer 3822 group mitsubishi microcomputers fig. 29 structure of serial i/o control registers brg count source se l ect i on bi t (css) 0: f(x in ) (f(x cin ) in low-speed mode) 1: f(x in )/4 (f(x cin )/4 in low-speed mode) serial i/o synchronization clock selection bit (scs) 0: brg output divided by 4 when clock synchronized serial i/o is selected. brg output divided by 16 when uart is selected. 1: external clock input when clock synchronized serial i/o is selected. external clock input divided by 16 when uart is selected. s rdy output enable bit (srdy) 0: p4 7 pin operates as ordinary i/o pin 1: p4 7 pin operates as s rdy output pin transmit interrupt source selection bit (tic) 0: interrupt when transmit buffer has emptied 1: interrupt when transmit shift operation is completed transmit enable bit (te) 0: transmit disabled 1: transmit enabled receive enable bit (re) 0: receive disabled 1: receive enabled serial i/o mode selection bit (siom) 0: asynchronous serial i/o (uart) 1: clock synchronous serial i/o serial i/o enable bit (sioe) 0: serial i/o disabled (pins p4 4 C p4 7 operate as ordinary i/o pins) 1: serial i/o enabled (pins p4 4 C p4 7 operate as serial i/o pins) s e r i a l i / o c o n t r o l r e g i s t e r ( s i o c o n : a d d r e s s 0 0 1 a 1 6 ) b7 b0 t r a n s m i t b u f f e r e m p t y f l a g ( t b e ) 0 : b u f f e r f u l l 1 : b u f f e r e m p t y r e c e i v e b u f f e r f u l l f l a g ( r b f ) 0 : b u f f e r e m p t y 1 : b u f f e r f u l l t r a n s m i t s h i f t r e g i s t e r s h i f t c o m p l e t i o n f l a g ( t s c ) 0 : t r a n s m i t s h i f t i n p r o g r e s s 1 : t r a n s m i t s h i f t c o m p l e t e d o v e r r u n e r r o r f l a g ( o e ) 0 : n o e r r o r 1 : o v e r r u n e r r o r p a r i t y e r r o r f l a g ( p e ) 0 : n o e r r o r 1 : p a r i t y e r r o r f r a m i n g e r r o r f l a g ( f e ) 0 : n o e r r o r 1 : f r a m i n g e r r o r s u m m i n g e r r o r f l a g ( s e ) 0 : ( o e ) u ( p e ) u ( f e ) = 0 1 : ( o e ) u ( p e ) u ( f e ) = 1 n o t u s e d ( r e t u r n s 1 w h e n r e a d ) s er i a l i / o status reg i ster (siosts : address 0019 16 ) b 7b0 u a r t c o n t r o l r e g i s t e r ( u a r t c o n : a d d r e s s 0 0 1 b 1 6 ) ch aracter l engt h se l ect i on bi t (chas) 0: 8 bits 1: 7 bits parity enable bit (pare) 0: parity checking disabled 1: parity checking enabled parity selection bit (pars) 0: even parity 1: odd parity stop bit length selection bit (stps) 0: 1 stop bit 1: 2 stop bits p4 5 /t x d p-channel output disable bit (poff) 0: cmos output (in output mode) 1: n-channel open-drain output (in output mode) not used (return 1 when read) b 7b0
33 single-chip 8-bit cmos microcomputer 3822 group mitsubishi microcomputers a-d converter [a-d conversion register (ad)] 0035 16 the a-d conversion register is a read-only register that contains the result of an a-d conversion. when reading this register during an a-d conversion, the previous conversion result is read. [a-d control register (adcon)] 0034 16 the a-d control register controls the a-d conversion process. bits 0 to 2 of this register select specific analog input pins. bit 3 signals the completion of an a-d conversion. the value of this bit remains at 0 during an a-d conversion, then changes to 1 when the a- d conversion is completed. writing 0 to this bit starts the a-d conversion. bit 4 controls the transistor which breaks the through current of the resistor ladder. when bit 5, which is the ad external trigger valid bit, is set to 1 , this bit enables a-d conversion even by a falling edge of an adt input. set ports which share with adt pins to input when using an a-d external trigger. [comparison voltage generator] the comparison voltage generator divides the voltage between av ss and v ref by 256, and outputs the divided voltages. [channel selector] the channel selector selects one of the input ports p6 7 /an 7 C p6 0 / an 0, and inputs it to the comparator. [comparator and control circuit] the comparator and control circuit compares an analog input volt- age with the comparison voltage and stores the result in the a-d conversion register. when an a-d conversion is completed, the control circuit sets the ad conversion completion bit and the ad interrupt request bit to 1 . note that the comparator is constructed linked to a capacitor, so set f(x in ) to at least 500 khz during a-d conversion. use the clock divided from the main clock x in as the internal clock . fig. 31 a-d converter block diagram fig. 30 structure of a-d control register a - d c o n t r o l r e g i s t e r ( a d c o n : a d d r e s s 0 0 3 4 1 6 ) a d c o n v e r s i o n c o m p l e t i o n b i t 0 : c o n v e r s i o n i n p r o g r e s s 1 : c o n v e r s i o n c o m p l e t e d a n a l o g i n p u t p i n s e l e c t i o n b i t s 0 0 0 : p 6 0 / a n 0 0 0 1 : p 6 1 / a n 1 0 1 0 : p 6 2 / a n 2 0 1 1 : p 6 3 / a n 3 1 0 0 : p 6 4 / a n 4 1 0 1 : p 6 5 / a n 5 1 1 0 : p 6 6 / a n 6 1 1 1 : p 6 7 / a n 7 v r e f i n p u t s w i t c h b i t 0 : o f f 1 : o n ad externa l tr i gger va lid bi t 0 : a-d external trigger invalid 1 : a-d external trigger valid b 7 b 0 i n t e r r u p t s o u r c e s e l e c t i o n b i t 0 : i n t e r r u p t r e q u e s t a t a - d c o n v e r s i o n c o m p l e t e d 1 : i n t e r r u p t r e q u e s t a t a d t i n p u t f a l l i n g n o t u s e d ( r e t u r n s 0 w h e n r e a d ) c omparato r a - d contro l c i rcu it a d t / a - d i n t e r r u p t r e q u e s t av s s v r e f p 6 0 / a n 0 d a t a b u s a - d c o n t r o l r e g i s t e r b 7 b 0 a - d convers i on register r es i stor l a dd e r c h a n n e l s e l e c t o r p 6 7 / a n 7 p 6 6 / a n 6 p 6 5 / a n 5 p 6 4 / a n 4 p 6 3 / a n 3 p 6 2 / a n 2 p 6 1 / a n 1 p 5 7 / a d t 8 3
34 single-chip 8-bit cmos microcomputer 3822 group mitsubishi microcomputers lcd drive control circuit the 3822 group has the built-in liquid crystal display (lcd) drive control circuit consisting of the following. lcd display ram segment output enable register lcd mode register selector timing controller common driver segment driver bias control circuit a maximum of 32 segment output pins and 4 common output pins can be used. up to 128 pixels can be controlled for lcd display. when the lcd fig. 32 structure of segment output enable register and lcd mode register enable bit is set to 1 after data is set in the lcd mode register, the segment output enable register and the lcd display ram, the lcd drive control circuit starts reading the display data automati- cally, performs the bias control and the duty ratio control, and displays the data on the lcd panel. table 11 maximum number of display pixels at each duty ratio duty ratio maximum number of display pixel 64 dots or 8 segment lcd 8 digits 96 dots or 8 segment lcd 12 digits 128 dots or 8 segment lcd 16 digits 2 3 4 l c d m o d e r e g i s t e r ( l m : a d d r e s s 0 0 3 9 1 6 ) segment output enable register (seg : address 0038 16 ) duty ratio selection bits 0 0 : not used 0 1 : 2 (use com 0 , com 1 ) 1 0 : 3 (use com 0 C com 2 ) 1 1 : 4 (use com 0 C com 3 ) bias control bit 0 : 1/3 bias 1 : 1/2 bias lcd enable bit 0 : lcd off 1 : lcd on not used (returns 0 when read) (do not write 1 to this bit) lcd circuit divider division ratio selection bits 0 0 : clock input 0 1 : 2 division of clock input 1 0 : 4 division of clock input 1 1 : 8 division of clock input lcdck count source selection bit (note) 0 : f(x cin )/32 1 : f(x in )/8192 (or f(x cin )/8192 in low-speed mode) n o t e : l c d c k i s a c l o c k f o r a l c d t i m i n g c o n t r o l l e r . segment output enable bit 0 0 : input port p3 4 C p3 7 1 : segment output seg 12 C seg 15 segment output enable bit 1 0 : i/o port p0 0 ,p0 1 1 : segment output seg 16 , seg 17 segment output enable bit 2 0 : i/o port p0 2 C p0 7 1 : segment output seg 18 C seg 23 segment output enable bit 3 0 : i/o port p1 0 ,p1 1 1 : segment output seg 24 , seg 25 segment output enable bit 4 0 : i/o port p1 2 1 : segment output seg 26 segment output enable bit 5 0 : i/o port p1 3 C p1 7 1 : segment output seg 27 C seg 31 not used (returns 0 when read) (do not write 1 to this bit.) b 7b 0 b 7b 0
35 single-chip 8-bit cmos microcomputer 3822 group mitsubishi microcomputers fig. 33 block diagram of lcd controller/driver c o m 0 c o m 1 c o m 2 c o m 3 v s s v l 1 v l 2 v l 3 s e g 3 s e g 2 s e g 1 s e g 0 1 0 l c d c k 2 2 p 1 7 / s e g 3 1 p 1 6 / s e g 3 0 p 3 4 / s e g 1 2 f ( x c i n ) / 3 2 f ( x i n ) / 8 1 9 2 ( o r f ( x c i n ) / 8 1 9 2 i n l o w - s p e e d m o d e ) d a t a b u s a d d r e s s 0 0 4 0 1 6 a d d r e s s 0 0 4 1 1 6 a d d r e s s 0 0 4 f 1 6 s e l e c t o r s e l e c t o r s e l e c t o r s e l e c t o r s e l e c t o r s e l e c t o r s e g m e n t d r i v e r s e g m e n t d r i v e r s e g m e n t d r i v e r s e g m e n t d r i v e r s e g m e n t d r i v e r s e g m e n t d r i v e r b i a s c o n t r o l l c d d i v i d e r t i m i n g c o n t r o l l e r c o m m o n d r i v e r d u t y r a t i o s e l e c t i o n b i t s c o m m o n d r i v e r c o m m o n d r i v e r c o m m o n d r i v e r b i a s c o n t r o l b i t l c d c i r c u i t d i v i d e r d i v i s i o n r a t i o s e l e c t i o n b i t s l c d c k c o u n t s o u r c e s e l e c t i o n b i t l c d d i s p l a y r a m l c d e n a b l e b i t
36 single-chip 8-bit cmos microcomputer 3822 group mitsubishi microcomputers bias control and applied voltage to lcd power input pins to the lcd power input pins (v l1 C v l3 ), apply the voltage shown in table 12 according to the bias value. select a bias value by the bias control bit (bit 2 of the lcd mode register). common pin and duty ratio control the common pins (com 0 C com 3 ) to be used are determined by duty ratio. select duty ratio by the duty ratio selection bits (bits 0 and 1 of the lcd mode register). fig. 34 example of circuit at each bias table 13 duty ratio control and common pins used duty ratio common pins used notes1: com 2 and com 3 are open. 2: com 3 is open. bit 1 bit 0 com 0 , com 1 (note 1) duty ratio selection bit 2 3 4 0 1 1 1 0 1 com 0 C com 2 (note 2) com 0 C com 3 table 12 bias control and applied voltage to v l1 ? l3 bias value 1/3 bias voltage value v l3 =v lcd v l2 =2/3 v lcd v l1 =1/3 v lcd note 1: v lcd is the maximum value of supplied voltage for the lcd panel. 1/2 bias v l3 =v lcd v l2 =v l1 =1/2 v lcd contrast control 1/2 bias 1/3 bias contrast control v l3 r 4 r5 r 4 = r 5 r 1 r 2 r3 r 1 = r 2 = r 3 v l2 v l1 v l 3 v l2 v l 1
37 single-chip 8-bit cmos microcomputer 3822 group mitsubishi microcomputers lcd display ram address 0040 16 to 004f 16 is the designated ram for the lcd dis- play. when 1 are written to these addresses, the corresponding segments of the lcd display panel are turned on. fig. 35 lcd display ram map lcd drive timing the lcdck timing frequency (lcd drive timing) is generated in- ternally and the frame frequency can be determined with the following equation; f(lcdck) = frame frequency = (frequency of count source for lcdck) (divider division ratio for lcd) f(lcdck) (duty ratio) b i t a d d r e s s 7 0 0 4 0 1 6 0 0 4 1 1 6 0 0 4 2 1 6 0 0 4 3 1 6 0 0 4 4 1 6 0 0 4 5 1 6 0 0 4 6 1 6 0 0 4 7 1 6 0 0 4 8 1 6 0 0 4 9 1 6 0 0 4 a 1 6 0 0 4 b 1 6 0 0 4 c 1 6 0 0 4 d 1 6 0 0 4 e 1 6 0 0 4 f 1 6 c o m 3 0 1 2 3 4 5 6 c o m 0 com 1 c o m 2 com 3 c o m 0 com 1 c o m 2 s e g 1 s e g 3 s e g 5 s e g 7 s e g 9 s e g 1 1 s e g 1 3 s e g 1 5 s e g 1 7 s e g 1 9 s e g 2 1 s e g 2 3 s e g 2 5 s e g 2 7 s e g 2 9 s e g 3 1 seg 0 seg 2 seg 4 seg 6 seg 8 seg 10 seg 12 seg 14 seg 16 seg 18 seg 20 seg 22 seg 24 seg 26 seg 28 seg 30
38 single-chip 8-bit cmos microcomputer 3822 group mitsubishi microcomputers fig. 36 lcd drive waveform (1/2 bias) i n t e r n a l l o g i c l c d c k t i m i n g 1 / 4 d u t y v o l t a g e l e v e l v l3 v l2 =v l1 v ss v l3 v ss c o m 0 c o m 1 c o m 2 c o m 3 seg 0 o f fon o f fon c o m 3 c o m 2 c o m 1 c o m 0 c o m 3 c o m 2 com 1 c o m 0 1/3 duty v l3 v l2 =v l1 v ss v l3 v ss off on on off on off 1 / 2 d u t y com 0 com 1 com 2 seg 0 c o m 0 com 1 seg 0 v l3 v l2 =v l1 v ss v l3 v ss off o n o f f on o f f on o f f o n c o m 0 c o m 2 c o m 1 c o m 0 com 2 c o m 1 com 0 c o m 2 com 1 com 0 com 1 c o m 0 com 1 com 0 com 1 com 0
39 single-chip 8-bit cmos microcomputer 3822 group mitsubishi microcomputers fig. 37 lcd drive waveform (1/3 bias) i n t e r n a l l o g i c l c d c k t i m i n g 1/4 duty v o l t a g e l e v e l v l 3 v s s c o m 0 c o m 1 c o m 2 c o m 3 seg 0 o f fo n o f fo n com 3 c o m 2 c o m 1 c o m 0 com 3 c o m 2 c o m 1 com 0 1/3 duty o f f on o no f f on o f f 1 / 2 d u t y com 0 c o m 1 c o m 2 s e g 0 c o m 0 c o m 1 s e g 0 off on off on off on off on v l3 v l 2 v s s v l 1 v l3 v l2 v s s v l1 v l 3 v ss v l3 v l 2 v ss v l 1 v l3 v s s c o m 0 c o m 2 c o m 1 c o m 0 c o m 2 c o m 1 com 0 c o m 2 c o m 1 c o m 0 c o m 1 c o m 0 c o m 1 c o m 0 com 1 c o m 0
40 single-chip 8-bit cmos microcomputer 3822 group mitsubishi microcomputers clock system output function the internal system clock can be output from port p4 1 by setting the output control register. set bit 1 of the port p4 direction reg- ister to 1 when outputting clock. fig. 38 structure of output control register o u t p u t c o n t r o l r e g i s t e r ( c k o u t : a d d r e s s 0 0 2 a 1 6 ) output control bit 0 : port function 1 : clock output not used (return 0 when read) b 7 b 0
41 single-chip 8-bit cmos microcomputer 3822 group mitsubishi microcomputers reset circuit to reset the microcomputer, reset pin should be held at an l level for 2 s or more. then the reset pin is returned to an h level (the power source voltage should be between v cc (min.) and 5.5 v, and the quartz-crystal oscillator should be stable), reset is released. after the reset is completed, the program starts from the address contained in address fffd 16 (high-order byte) and ad- dress fffc 16 (low-order byte). make sure that the reset input voltage meets v il spec. when a power source voltage passes v cc (min.). fig. 39 reset circuit example fig. 40 reset sequence p o w e r o n p o w e r s o u r c e v o l t a g e reset input voltage p o w e r s o u r c e v o l t a g e d e t e c t i o n c i r c u i t v i l s p e c . 0 v 0 v v cc r e s e t v cc r e s e t r e s e t i n t e r n a l r e s e t a d d r e s s d a t a s y n c x in x i n : a b o u t 8 0 0 0 c y c l e s r e s e t a d d r e s s f r o m v e c t o r t a b l e n o t e s 1 : t h e f r e q u e n c y r e l a t i o n o f f ( x i n ) a n d f ( ) i s f ( x i n ) = 8 ? f ( ) 2 : t h e q u e s t i o n m a r k s ( ? ) i n d i c a t e a n u n d e f i n e d s t a t e t h a t d e p e n d s o n t h e p r e v i o u s s t a t e . fffc fffd a d h , a d l ad l ad h ????
42 single-chip 8-bit cmos microcomputer 3822 group mitsubishi microcomputers fig. 41 initial status of microcomputer after reset p o r t p 0 d i r e c t i o n r e g i s t e r p o r t p 1 d i r e c t i o n r e g i s t e r p o r t p 2 d i r e c t i o n r e g i s t e r p o r t p 4 d i r e c t i o n r e g i s t e r p o r t p 5 d i r e c t i o n r e g i s t e r p o r t p 6 d i r e c t i o n r e g i s t e r p o r t p 7 d i r e c t i o n r e g i s t e r p u l l r e g i s t e r a p u l l r e g i s t e r b s i r i a l i / o s t a t u s r e g i s t e r s i r i a l i / o c o n t r o l r e g i s t e r u a r t c o n t r o l r e g i s t e r t i m e r x ( l o w ) t i m e r x ( h i g h ) t i m e r y ( l o w ) t i m e r y ( h i g h ) t i m e r 1 t i m e r 2 t i m e r 3 t i m e r x m o d e r e g i s t e r t i m e r y m o d e r e g i s t e r t i m e r 1 2 3 m o d e r e g i s t e r o u t p u t c o n t r o l r e g i s t e r a - d c o n t r o l r e g i s t e r s e g m e n t o u t p u t e n a b l e r e g i s t e r l c d m o d e r e g i s t e r i n t e r r u p t e d g e s e l e c t i o n r e g i s t e r c p u m o d e r e g i s t e r i n t e r r u p t r e q u e s t r e g i s t e r 1 i n t e r r u p t r e q u e s t r e g i s t e r 2 i n t e r r u p t c o n t r o l r e g i s t e r 1 i n t e r r u p t c o n t r o l r e g i s t e r 2 p r o c e s s o r s t a t u s r e g i s t e r p r o g r a m c o u n t e r note: the contents of all other registers and ram are undefined after reset, so they must be initialized by software. ? : undefined r e g i s t e r c o n t e n t s a d d r e s s 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 f f 1 6 f f 1 6 f f 1 6 f f 1 6 f f 1 6 0 1 1 6 f f 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 c o n t e n t s o f a d d r e s s f f f d 1 6 c o n t e n t s o f a d d r e s s f f f c 1 6 ( 1 ) ( 2 ) ( 3 ) ( 4 ) ( 5 ) ( 6 ) ( 7 ) ( 8 ) ( 9 ) ( 1 0 ) ( 1 1 ) ( 1 2 ) ( 1 3 ) ( 1 4 ) ( 1 5 ) ( 1 6 ) ( 1 7 ) ( 1 8 ) ( 1 9 ) ( 2 0 ) ( 2 1 ) ( 2 2 ) ( 2 3 ) ( 2 4 ) ( 2 5 ) ( 2 6 ) ( 2 7 ) ( 2 8 ) ( 2 9 ) ( 3 0 ) ( 3 1 ) ( 3 2 ) ( 3 3 ) ( 3 4 ) 0 0 0 1 1 6 0 0 0 3 1 6 0 0 0 5 1 6 0 0 0 9 1 6 0 0 0 b 1 6 0 0 0 d 1 6 0 0 0 f 1 6 0 0 1 6 1 6 0 0 1 7 1 6 0 0 1 9 1 6 0 0 1 a 1 6 0 0 1 b 1 6 0 0 2 0 1 6 0 0 2 1 1 6 0 0 2 2 1 6 0 0 2 3 1 6 0 0 2 4 1 6 0 0 2 5 1 6 0 0 2 6 1 6 0 0 2 7 1 6 0 0 2 8 1 6 0 0 2 9 1 6 0 0 2 a 1 6 0 0 3 4 1 6 0 0 3 8 1 6 0 0 3 9 1 6 0 0 3 a 1 6 0 0 3 b 1 6 0 0 3 c 1 6 0 0 3 d 1 6 0 0 3 e 1 6 0 0 3 f 1 6 ( p s ) ( p c h ) ( p c l ) 01001 00 0 00001 00 0 11100 00 0 10000 00 0 00001 11 0 ????? ?? 1
43 single-chip 8-bit cmos microcomputer 3822 group mitsubishi microcomputers clock generating circuit the 3822 group has two built-in oscillation circuits. an oscillation circuit can be formed by connecting a resonator between x in and x out (x cin and x cout ). use the circuit constants in accordance with the resonator manufacturer's recommended values. no exter- nal resistor is needed between x in and x out since a feed-back resistor exists on-chip. however, an external feed-back resistor is needed between x cin and x cout . to supply a clock signal externally, input it to the x in pin and make the x out pin open. the sub-clock x cin -x cout oscillation circuit cannot directly input clocks that are externally generated. accord- ingly, be sure to cause an external resonator to oscillate. immediately after poweron, only the x in oscillation circuit starts oscillating, and x cin and x cout pins function as i/o ports. frequency control (1) middle-speed mode the internal clock is the frequency of x in divided by 8. after reset, this mode is selected. (2) high-speed mode the internal clock is half the frequency of x in . (3) low-speed mode the internal clock is half the frequency of x cin . a low-power consumption operation can be realized by stopping the main clock x in in this mode. to stop the main clock, set bit 5 of the cpu mode register to 1 . when the main clock x in is restarted, set enough time for oscil- lation to stabilize by programming. note: if you switch the mode between middle/high-speed and low- speed, stabilize both x in and x cin oscillations. the sufficient time is required for the sub-clock to stabilize, es- pecially immediately after poweron and at returning from stop mode. when switching the mode between middle/high- speed and low-speed, set the frequency on condition that f(x in ) > 3f(x cin ). fig. 42 ceramic resonator circuit fig. 43 external clock input circuit oscillation control (1) stop mode if the stp instruction is executed, the internal clock stops at an h level, and x in and x cin oscillators stop. timer 1 is set to ff 16 and timer 2 is set to 01 16 . either x in or x cin divided by 16 is input to timer 1 as count source, and the output of timer 1 is connected to timer 2. the bits of the timer 123 mode register except bit 4 are cleared to 0 . set the timer 1 and timer 2 interrupt enable bits to disabled ( 0 ) be- fore executing the stp instruction. oscillator restarts at reset or when an external interrupt is received, but the internal clock is not supplied to the cpu until timer 2 underflows. this allows timer for the clock circuit oscillation to stabilize. (2) wait mode if the wit instruction is executed, the internal clock stops at an h level. the states of x in and x cin are the same as the state be- fore the executing the wit instruction. the internal clock restarts at reset or when an interrupt is received. since the oscillator does not stop, normal operation can be started immediately after the clock is restarted. x c i n x c o u t x i n x o u t c i n c out c cin c c o u t r f rd x i n e x t e r n a l o s c i l l a t i o n c i r c u i t o p e n v c c v s s c c i n c cout rf r d x c i n x c o u t x o u t
44 single-chip 8-bit cmos microcomputer 3822 group mitsubishi microcomputers fig.44 clock generating circuit block diagram w i t i n s t r u c t i o n stp i nstruct i on ti m i ng (internal system clock) s r q stp i nstruct i on s r q m a i n c l oc k stop bi t s r q t i m e r 2 t i m e r 1 1/2 1/4 x i n x o u t x c o u t x c i n i n t e r r u p t r e q u e s t r eset p o r t x c s w i t c h b i t 1 0 t i m e r 1 c o u n t s o u r c e s e l e c t i o n b i t t i m e r 2 c o u n t s o u r c e s e l e c t i o n b i t l o w - s p e e d m o d e middl e-/ hi g h -spee d mo d e i n t e r n a l s y s t e m c l o c k s e l e c t i o n b i t ( n o t e ) m i d d l e - s p e e d m o d e hi g h -spee d mo d e or low-speed mode n ote : wh en us i ng t h e l ow-spee d mo d e, set t h e port x c sw i tc h bi t to 1 . m a i n c l oc k di v i s i on rat i o se l ect i on bi t 1 0 1 0 1 0 i n t e r r u p t d i s a b l e f l a g i 1 / 2 1 0
45 single-chip 8-bit cmos microcomputer 3822 group mitsubishi microcomputers fig. 45 state transitions of system clock n o t e s 1 : s w i t c h t h e m o d e b y t h e a l l o w s s h o w n b e t w e e n t h e m o d e b l o c k s . ( d o n o t s w i t c h b e t w e e n t h e m o d e d i r e c t l y w i t h o u t a n a l l o w . ) 2 : t h e a l l m o d e s c a n b e s w i t c h e d t o t h e s t o p m o d e o r t h e w a i t m o d e a n d r e t u r n e d t o t h e s o u r c e m o d e w h e n t h e s t o p m o d e o r t h e w a i t m o d e i s e n d e d . 3 : t i m e r a n d l c d o p e r a t e i n t h e w a i t m o d e . 4 : w h e n t h e s t o p m o d e i s e n d e d , a d e l a y o f a p p r o x i m a t e l y 1 m s o c c u r s a u t o m a t i c a l l y b y t i m e r 1 a n d t i m e r 2 i n m i d d l e - / h i g h - s p e e d m o d e . 5 : w h e n t h e s t o p m o d e i s e n d e d , a d e l a y o f a p p r o x i m a t e l y 0 . 2 5 s o c c u r s a u t o m a t i c a l l y b y t i m e r 1 a n d t i m e r 2 i n l o w - s p e e d m o d e . 6 : w a i t u n t i l o s c i l l a t i o n s t a b i l i z e s a f t e r o s c i l l a t i n g t h e m a i n c l o c k x i n b e f o r e t h e s w i t c h i n g f r o m t h e l o w - s p e e d m o d e t o m i d d l e - / h i g h - s p e e d m o d e . 7 : t h e e x a m p l e a s s u m e s t h a t 8 m h z i s b e i n g a p p l i e d t o t h e x i n p i n a n d 3 2 k h z t o t h e x c i n p i n . i n d i c a t e s t h e i n t e r n a l c l o c k . cm 4 : p ort x c sw i tc h bi t 0: i/o port 1: x cin , x cout cm 5 : main clock (x in C x out ) stop bit 0: oscillating 1: stopped cm 6 : main clock division ratio selection bit 0: f(x in )/2 (high-speed mode) 1: f(x in )/8 (middle-speed mode) cm 7 : internal system clock selection bit 0: x in C x out selected (middle-/high-speed mode) 1: x cin C x cout selected (low-speed mode ) cpu mo d e reg i ster (cpum : address 003b 16 ) b 7 b 4 r ese t cm 6 0 1 c m 4 0 1 c m 7 = 0 ( 8 m h z s e l e c t e d ) c m 6 = 1 ( m i d d l e - s p e e d ) c m 5 = 0 ( 8 m h z o s c i l l a t i n g ) c m 4 = 0 ( 3 2 k h z s t o p p e d ) m i d d l e - s p e e d m o d e ( f ( ) = 1 m h z ) c m 7 = 0 ( 8 m h z s e l e c t e d ) c m 6 = 1 ( m i d d l e - s p e e d ) c m 5 = 0 ( 8 m h z o s c i l l a t i n g ) c m 4 = 1 ( 3 2 k h z o s c i l l a t i n g ) m i d d l e - s p e e d m o d e ( f ( ) = 1 m h z ) c m 7 = 0 ( 8 m h z s e l e c t e d ) c m 6 = 0 ( h i g h - s p e e d ) c m 5 = 0 ( 8 m h z o s c i l l a t i n g ) c m 4 = 0 ( 3 2 k h z s t o p p e d ) high-speed mode (f( ) = 4 mhz) cm 7 = 0 (8 mhz selected) cm 6 = 0 (high-speed) cm 5 = 0 (8 mhz oscillating) cm 4 = 1 (32 khz oscillating) high-speed mode (f( ) = 4 mhz) c m 7 = 1 ( 3 2 k h z s e l e c t e d ) c m 6 = 1 ( m i d d l e - s p e e d ) c m 5 = 0 ( 8 m h z o s c i l l a t i n g ) c m 4 = 1 ( 3 2 k h z o s c i l l a t i n g ) l o w - s p e e d m o d e ( f ( ) = 1 6 k h z ) cm 7 = 1 (32 khz selected) cm 6 = 0 (high-speed) cm 5 = 0 (8 mhz oscillating) cm 4 = 1 (32 khz oscillating) l o w - s p e e d m o d e ( f ( ) = 1 6 k h z ) c m 7 = 1 ( 3 2 k h z s e l e c t e d ) c m 6 = 1 ( m i d d l e - s p e e d ) c m 5 = 1 ( 8 m h z s t o p p e d ) c m 4 = 1 ( 3 2 k h z o s c i l l a t i n g ) l o w - s p e e d m o d e ( f ( ) = 1 6 k h z ) c m 7 = 1 ( 3 2 k h z s e l e c t e d ) c m 6 = 0 ( h i g h - s p e e d ) c m 5 = 1 ( 8 m h z s t o p p e d ) c m 4 = 1 ( 3 2 k h z o s c i l l a t i n g ) l o w - s p e e d m o d e ( f ( ) = 1 6 k h z ) cm 6 0 1 cm 6 0 1 cm 6 0 1 c m 4 0 1 c m 7 0 1 c m 7 0 1 c m 5 0 1 c m 5 0 1 c m 4 c m 6 0 1 0 1 c m 4 c m 6 0 1 1 0 c m 5 c m 6 0 1 0 1 c m 5 c m 6 0 1 1 0
46 single-chip 8-bit cmos microcomputer 3822 group mitsubishi microcomputers notes on programming processor status register the contents of the processor status register (ps) after a reset are undefined, except for the interrupt disable flag (i) which is 1 . af- ter a reset, initialize flags which affect program execution. in particular, it is essential to initialize the index x mode (t) and the decimal mode (d) flags because of their effect on calculations. interrupt the contents of the interrupt request bits do not change immedi- ately after they have been written. after writing to an interrupt request register, execute at least one instruction before perform- ing a bbc or bbs instruction. decimal calculations ? to calculate in decimal notation, set the decimal mode flag (d) to 1 , then execute an adc or sbc instruction. after executing an adc or sbc instruction, execute at least one instruction be- fore executing a sec, clc, or cld instruction. ? in decimal mode, the values of the negative (n), overflow (v), and zero (z) flags are invalid. timers if a value n (between 0 and 255) is written to a timer latch, the fre- quency division ratio is 1/(n + 1). multiplication and division instructions the index mode (t) and the decimal mode (d) flags do not affect the mul and div instruction. the execution of these instructions does not change the contents of the processor status register. ports the contents of the port direction registers cannot be read. the following cannot be used: ? the data transfer instruction (lda, etc.) ? the operation instruction when the index x mode flag (t) is 1 ? the addressing mode which uses the value of a direction regis- ter as an index ? the bit-test instruction (bbc or bbs, etc.) to a direction register ? the read-modify-write instruction (ror, clb, or seb, etc.) to a direction register use instructions such as ldm and sta, etc., to set the port direc- tion registers. serial i/o in clock synchronous serial i/o, if the receive side is using an ex- ternal clock and it is to output the s rdy signal, set the transmit enable bit, the receive enable bit, and the s rdy output enable bit to 1 . serial i/o continues to output the final bit from the t x d pin after transmission is completed. a-d converter the comparator uses internal capacitors whose charge will be lost if the clock frequency is too low. make sure that f(x in ) is at least 500 khz during an a-d conver- sion. do not execute the stp or wit instruction during an a-d conver- sion. instruction execution time the instruction execution time is obtained by multiplying the fre- quency of the internal clock by the number of cycles needed to execute an instruction. the number of cycles required to execute an instruction is shown in the list of machine instructions. the frequency of the internal clock is half of the x in frequency.
47 single-chip 8-bit cmos microcomputer 3822 group mitsubishi microcomputers notes on use countermeasures against noise (1) shortest wiring length ? wiring for reset pin make the length of wiring which is connected to the reset pin as short as possible. especially, connect a capacitor across the reset pin and the v ss pin with the shortest possible wiring (within 20mm). reason the width of a pulse input into the reset pin is determined by the timing necessary conditions. if noise having a shorter pulse width than the standard is input to the reset pin, the reset is released before the internal state of the microcomputer is com- pletely initialized. this may cause a program runaway. (2) connection of bypass capacitor across v ss line and v cc line in order to stabilize the system operation and avoid the latch-up, connect an approximately 0.1 f bypass capacitor across the v ss line and the v cc line as follows: ? connect a bypass capacitor across the v ss pin and the v cc pin at equal length. ? connect a bypass capacitor across the v ss pin and the v cc pin with the shortest possible wiring. ? use lines with a larger diameter than other signal lines for v ss line and v cc line. ? connect the power source wiring via a bypass capacitor to the v ss pin and the v cc pin. ? wiring for clock input/output pins ? make the length of wiring which is connected to clock i/o pins as short as possible. ? make the length of wiring (within 20 mm) across the grounding lead of a capacitor which is connected to an oscillator and the v ss pin of a microcomputer as short as possible. ? separate the v ss pattern only for oscillation from other v ss patterns. reason if noise enters clock i/o pins, clock waveforms may be de- formed. this may cause a program failure or program runaway. also, if a potential difference is caused by the noise between the v ss level of a microcomputer and the v ss level of an oscil- lator, the correct clock will not be input in the microcomputer. reset reset circuit noise v ss v ss reset circuit v ss reset v ss n.g. o.k. noise x in x out v ss x in x out v ss n.g. o.k. v ss v cc aa aa aa aa aa aa v ss v cc aa aa aa aa aa aa aa aa aa n.g. o.k. fig. 47 wiring for clock i/o pins fig. 46 wiring for the reset pin fig. 48 bypass capacitor across the v ss line and the v cc line
48 single-chip 8-bit cmos microcomputer 3822 group mitsubishi microcomputers (3) oscillator concerns in order to obtain the stabilized operation clock on the user system and its condition, contact the oscillator manufacturer and select the oscillator and oscillation circuit constants. be careful espe- cially when range of votage and temperature is wide. also, take care to prevent an oscillator that generates clocks for a microcomputer operation from being affected by other signals. ? ? ? ? fig. 50 wiring for the v pp pin of one time prom fig. 49 wiring for a large current signal line/ wiring of signal lines where potential levels change frequently p4 0 /v pp v ss about 5k ? ? note: even when a circuit which included an approximately 5 k ? electric characteristic differences between mask rom and one time prom version mcus there are differences in electric characteristics, operation margin, noise immunity, and noise radiation between mask rom and one time prom version mcus due to the difference in the manufac- turing processes. when manufacturing an application system with the one time prom version and then switching to use of the mask rom version, please perform sufficient evaluations for the commercial samples of the mask rom version. x in x out v ss microcomputer mutual inductance large current gnd m x in x out v ss cntr do not cross n.g.
49 single-chip 8-bit cmos microcomputer 3822 group mitsubishi microcomputers data required for mask orders the following are necessary when ordering a mask rom produc- tion: 1.mask rom order confirmation form ? ? ? mitsubishi mcu technical information homepage (http://www.infomicom.maec.co.jp/). rom programming method the built-in prom of the blank one time prom version and built- in eprom version can be read or programmed with a general- purpose prom programmer using a special programming adapter. set the address of prom programmer in the user rom area. table 14 programming adapter the prom of the blank one time prom version is not tested or screened in the assembly process and following processes. to en- sure proper operation after programming, the procedure shown in figure 51 is recommended to verify programming. fig. 51 programming and testing of one time prom version package 80p6n-a 80p6s-a 80p6q-a 80d0 name of programming adapter pca4738f-80a pca4738g-80a pca4738h-80a pca4738l-80a p r o g r a m m i n g w i t h p r o m p r o g r a m m e r screening (caution) (150
50 single-chip 8-bit cmos microcomputer 3822 group mitsubishi microcomputers v o v o pd topr tstg C0.3 to 7.0 v power source voltage input voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 4 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 p6 0 Cp6 7 , p7 0 , p7 1 v cc v i symbol parameter conditions ratings unit all voltages are based on v ss . output transistors are cut off. v i v i v i v i v o v o v o input voltage v l1 input voltage v l2 input voltage v l3 input voltage reset, x in output voltage p0 0 Cp0 7 , p1 0 Cp1 7 output voltage p3 4 Cp3 7 output voltage p2 0 Cp2 7 , p4 1 Cp4 7 ,p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 , p7 1 output voltage seg 0 Cseg 11 output voltage x out power dissipation operating temperature storage temperature at output port at segment output at segment output C0.3 to v cc +0.3 C0.3 to v l2 v l1 to v l3 v l2 to v cc +0.3 C0.3 to v cc +0.3 C0.3 to v cc +0.3 C0.3 to v l3 +0.3 C0.3 to v l3 +0.3 C0.3 to v cc +0.3 C0.3 to v l3 +0.3 C0.3 to v cc +0.3 300 C20 to 85 C40 to 125 v v v v v v v v v v v mw c c ta = 25c table 16 recommended operating conditions (standard, one time prom version) (v cc = 2.5 to 5.5 v, ta = C20 to 85 c, unless otherwise noted) power source voltage a-d conversion reference voltage analog power source voltage analog input voltage an 0 Can 7 h input voltage p0 0 Cp0 7 , p1 0 Cp1 7 ,p3 4 Cp3 7 , p4 0 , p4 1 , p4 5 , p4 7 , p5 2 , p5 3, p5 6, p6 0 Cp6 7, p7 0 ,p7 1 (cm 4 = 0) h input voltage p2 0 Cp2 7 , p4 2 Cp4 4 ,p4 6 ,p5 0 , p5 1 , p5 4 , p5 5 , p5 7 h input voltage reset h input voltage x in l input voltage p0 0 Cp0 7 , p1 0 Cp1 7 ,p3 4 Cp3 7 , p4 0 , p4 1 , p4 5 , p4 7 , p5 2 , p5 3, p5 6, p6 0 Cp6 7, p7 0 ,p7 1 (cm 4 = 0) l input voltage p2 0 Cp2 7 , p4 2 Cp4 4 ,p4 6 ,p5 0 , p5 1 , p5 4 , p5 5 , p5 7 l input voltage reset l input voltage x in 5.5 5.5 5.5 v cc v cc v cc v cc v cc v cc 0.3 v cc 0.2 v cc 0.2 v cc 0.2 v cc v cc v ss v ref av ss v ia v ih v ih v ih v ih v il v il v il v il symbol parameter limits min. v v v v v v v v v v v v v unit 4.0 2.5 2.5 2.0 av ss 0.7v cc 0.8v cc 0.8v cc 0.8v cc 0 0 0 0 5.0 5.0 5.0 0 0 typ. max. power source voltage high-speed mode f(x in ) = 8 mhz middle-speed mode f(x in ) = 8 mhz low-speed mode table 15 absolute maximum ratings (standard, one time prom version)
51 single-chip 8-bit cmos microcomputer 3822 group mitsubishi microcomputers p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 (note 1) p4 1 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7, p7 0 , p7 1 (note 1) p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 (note 1) p4 1 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7, p7 0 , p7 1 (note 1) p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 (note 1) p4 1 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7, p7 0 , p7 1 (note 1) p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 (note 1) p4 1 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7, p7 0 , p7 1 (note 1) p0 0 Cp0 7 , p1 0 Cp1 7 (note 2) p2 0 Cp2 7 , p4 1 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7, p7 0 , p7 1 (note 2) p0 0 Cp0 7 , p1 0 Cp1 7 (note 2) p2 0 Cp2 7 , p4 1 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7, p7 0 , p7 1 (note 2) p0 0 Cp0 7 , p1 0 Cp1 7 (note 3) p2 0 Cp2 7 , p4 1 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7, p7 0 , p7 1 (note 3) p0 0 Cp0 7 , p1 0 Cp1 7 (note 3) p2 0 Cp2 7 , p4 1 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7, p7 0 , p7 1 (note 3) C40 C40 40 40 C20 C20 20 20 C2 C5 (v cc = 2.5 to 5.5 v, ta = C20 to 85 c, unless otherwise noted) notes 1: the total output current is the sum of all the currents flowing through all the applicable ports. the total average current is an average value mea- sured over 100 ms. the total peak current is the peak value of all the currents. 2: the peak output current is the peak current flowing in each port. 3: the average output current is an average value measured over 100 ms. 4: when the oscillation frequency has a duty cycle of 50 %. 5: when using the microcomputer in low-speed mode, make sure that the sub-clock input oscillation frequency on condition that f(x cin ) < f(x in )/3. h total peak output current h total peak output current l total peak output current l total peak output current h total average output current h total average output current l total average output current l total average output current h peak output current h peak output current i oh(peak) i oh(peak) i ol(peak) i ol(peak) i oh(avg) i oh(avg) i ol(avg) i ol(avg) i oh(peak) i oh(peak) symbol parameter limits min. ma ma ma ma ma ma ma ma ma ma unit typ. max. i ol(peak) i ol(peak) i oh(avg) i oh(avg) i ol(avg) 5 10 C1.0 C2.5 ma ma ma ma ma ma l peak output current l peak output current 2.5 5.0 4.0 (2 ? v cc)-4 8.0 (4 ? v cc)-8 8.0 50 h average output current h average output current l average output current l average output current input frequency for timers x and y (duty cycle 50%) i ol(avg) f(cntr 0 ) f(cntr 1 ) mhz mhz mhz mhz mhz khz (4.0 v v cc 5.5 v) (2.5 v v cc 4.0 v) 32.768 high-speed mode (4.0 v v cc 5.5 v) high-speed mode (2.5 v v cc 4.0 v) middle-speed mode main clock input oscillation frequency (note 4) sub-clock input oscillation frequency (notes 4, 5) f(x in ) f(x cin ) table 17 recommended operating conditions (standard, one time prom version)
52 single-chip 8-bit cmos microcomputer 3822 group mitsubishi microcomputers i ol = 10 ma i ol = 2.5 ma i ol = 2.5 ma v cc = 2.5 v i ol = 5 ma i ol = 1.25 ma i ol = 1.25 ma v cc = 2.5 v v ol i oh = C2.5 ma i oh = C0.6 ma v cc = 2.5 v i oh = C5 ma i oh = C1.25 ma i oh = C1.25 ma v cc = 2.5 v v v cc C2.0 h output voltage p0 0 Cp0 7 , p1 0 Cp1 7 symbol parameter limits min. unit 0.5 typ. max. test conditions v oh 2.0 0.5 (v cc =4.0 to 5.5 v, ta = C20 to 85c, unless otherwise noted) reset : v cc = 2.5 v to 5.5 v v i = v cc pull-downs off v cc = 5 v, v i = v cc pull-downs on v cc = 3 v, v i = v cc pull-downs on v i = v cc h output voltage p2 0 Cp2 7 , p4 1 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 , p7 1 (note) l output voltage p0 0 Cp0 7 , p10Cp17 l output voltage p2 0 Cp2 7 , p4 1 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 , p7 1 (note) hysteresis int 0 Cint 3 , adt, cntr 0, cntr 1, p2 0 Cp2 7 hysteresis s clk , r x d hysteresis reset h input current p0 0 Cp0 7 , p1 0 Cp1 7 , p3 4 Cp3 7 h input current p2 0 Cp2 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 , p7 1 (note) v oh v ol v t+ C v tC v t+ C v tC v t+ C v tC i ih i ih i ih v cc C2.0 v cc C0.5 30 6.0 C30 C6.0 0.5 0.5 70 2.0 0.5 45 140 5.0 5.0 C5.0 C5.0 C140 C45 v v v v v v v v v i ih i il v cc C1.0 v cc C1.0 v v v 1.0 v 1.0 5.0 a 25 v i = v cc v i = v cc v i = v ss v i = v ss pull-ups off v cc = 5 v, v i = v ss pull-ups on v cc = 3 v, v i = v ss pull-ups on v i = v ss v i = v ss h input current reset h input current x in l input current p0 0 Cp0 7 , p1 0 Cp1 7 , p3 4 Cp3 7 ,p4 0 l input current p2 0 Cp2 7 , p4 1 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 , p7 1 (note) l input current reset l input current x in 4.0 C5.0 C70 a a a a a a a a a a a i il i il i il C25 C4.0 note: when 1 is set to port x c switch bit (bit 4 at address 003b 16 ) of the cpu mode register, the drive ability of port p7 0 is different from the value above mentioned. table 18 electrical characteristics (standard, one time prom version)
53 single-chip 8-bit cmos microcomputer 3822 group mitsubishi microcomputers (v cc = 2.5 to 5.5 v, ta = C20 to 85 c, unless otherwise noted) v 5.5 ? high-speed mode, v cc = 5 v f(x in ) = 8 mhz f(x cin ) = 32.768 khz output transistors off a-d converter in operating ? high-speed mode, v cc = 5 v f(x in ) = 8 mhz (in wit state) f(x cin ) = 32.768 khz output transistors off a-d converter stopped ? low-speed mode, v cc = 5 v, ta 55c f(x in ) = stopped f(x cin ) = 32.768 khz output transistors off ? low-speed mode, v cc = 5 v, ta = 25c f(x in ) = stopped f(x cin ) = 32.768 khz (in wit state) output transistors off ? low-speed mode, v cc = 3 v, ta 55c f(x in ) = stopped f(x cin ) = 32.768 khz output transistors off ? low-speed mode, v cc = 3 v, ta = 25c f(x in ) = stopped f(x cin ) = 32.768 khz (in wit state) output transistors off all oscillation stopped (in stp state) output transistors off symbol parameter limits min. unit typ. max. ta = 25 c ta = 85 c test conditions i cc power source current 6.4 v ram ram retention voltage at clock stop mode 2.0 1.6 25 7.0 15 4.5 0.1 3.2 36 14 22 9.0 1.0 10 ma a a a a a ma 13 (v cc = 4.0 to 5.5 v, v ss = 0 v, ta = C20 to 85 c, 4 mhz f(x in ) 8 mhz, middle-/high-speed mode, unless otherwise noted) symbol parameter limits min. unit typ. max. test conditions C resolution absolute accuracy (excluding quantization error) v cc = v ref = 5v f(x in ) = 8 mhz v ref = 5 v 12 bits lsb 35 150 8 2 note: when an internal trigger is used in middle-speed mode, it is 14 s. s conversion time ladder resistor reference power source input current C t conv r ladder i vref k ? a analog port input current i ia a 12.5 (note) 100 200 5.0 50 table 19 electrical characteristics (standard, one time prom version) table 20 a-d converter characteristics (standard, one time prom version)
54 single-chip 8-bit cmos microcomputer 3822 group mitsubishi microcomputers (v cc = 4.0 to 5.5 v, v ss = 0 v, ta = C20 to 85 c, unless otherwise noted) 2 125 45 40 250 105 105 80 80 800 370 370 220 100 note: when bit 6 of address 001a 16 is 1 (clock synchronous). divide this value by four when bit 6 of address 001a 16 is 0 (uart). reset input l pulse width main clock input cycle time (x in input) main clock input h pulse width main clock input l pulse width cntr 0 , cntr 1 input cycle time cntr 0 , cntr 1 input h pulse width cntr 0 , cntr 1 input l pulse width int 0 to int 3 input h pulse width int 0 to int 3 input l pulse width serial i/o clock input cycle time (note) serial i/o clock input h pulse width (note) serial i/o clock input l pulse width (note) serial i/o input set up time serial i/o input hold time t w(reset) t c(x in ) t wh(x in ) t wl(x in ) t c(cntr) t wh(cntr) t wl(cntr) t wh(int) t wl(int) t c(s clk ) t wh(s clk ) t wl(s clk ) t su(r x dCs clk ) t h(s clk Cr x d) symbol parameter limits min. s ns ns ns ns ns ns ns ns ns ns ns ns ns unit typ. max. (v cc = 2.5 to 4.0 v, v ss = 0 v, ta = C20 to 85 c, unless otherwise noted) 2 125 45 40 500/(v cc -2) 250/(v cc -2)-20 250/(v cc -2)-20 230 230 2000 950 950 400 200 reset input l pulse width main clock input cycle time (x in input) main clock input h pulse width main clock input l pulse width cntr 0 , cntr 1 input cycle time cntr 0 , cntr 1 input h pulse width cntr 0 , cntr 1 input l pulse width int 0 to int 3 input h pulse width int 0 to int 3 input l pulse width serial i/o clock input cycle time (note) serial i/o clock input h pulse width (note) serial i/o clock input l pulse width (note) serial i/o input set up time serial i/o input hold time t w(reset) t c(x in ) t wh(x in ) t wl(x in ) t c(cntr) t wh(cntr) t wl(cntr) t wh(int) t wl(int) t c(s clk ) t wh(s clk ) t wl(s clk ) t su(r x dCs clk ) t h(s clk Cr x d) symbol parameter limits min. s ns ns ns ns ns ns ns ns ns ns ns ns ns unit typ. max. note: when bit 6 of address 001a 16 is 1 (clock synchronous). divide this value by four when bit 6 of address 001a 16 is 0 (uart). table 21 timing requirements 1 (standard, one time prom version) table 22 timing requirements 2 (standard, one time prom version)
55 single-chip 8-bit cmos microcomputer 3822 group mitsubishi microcomputers (v cc = 4.0 to 5.5 v, v ss = 0 v, ta = C20 to 85 c, unless otherwise noted) notes 1: when the p4 5 /t x d p-channel output disable bit of the uart control register (bit 4 of address 001b 16 ) is 0. 2: x out and x cout pins are excluded. serial i/o clock output h pulse width serial i/o clock output l pulse width serial i/o output delay time (note 1) serial i/o output valid time (note 1) serial i/o clock output rising time serial i/o clock output falling time cmos output rising time (note 2) cmos output falling time (note 2) 140 30 30 30 30 symbol parameter limits min. ns ns ns ns ns ns ns ns unit t c (s clk )/2C30 t c (s clk )/2C30 C30 10 10 typ. max. t wh(s clk ) t wl(s clk ) t d(s clk Ct x d) t v(s clk Ct x d) t r(s clk ) t f(s clk ) t r(cmos) t f(cmos) (v cc = 2.5 to 4.0 v, v ss = 0 v, ta = C20 to 85 c, unless otherwise noted) ns ns ns ns ns ns ns ns unit notes 1: when the p4 5 /t x d p-channel output disable bit of the uart control register (bit 4 of address 001b 16 ) is 0. 2: x out and x cout pins are excluded. serial i/o clock output h pulse width serial i/o clock output l pulse width serial i/o output delay time (note 1) serial i/o output valid time (note 1) serial i/o clock output rising time serial i/o clock output falling time cmos output rising time (note 2) cmos output falling time (note 2) 350 50 50 50 50 symbol parameter limits min. t c (s clk )/2C50 t c (s clk )/2C50 C30 20 20 max. t wh(s clk ) twl(s clk ) t d(s clk Ct x d) t v(s clk Ct x d) t r(s clk ) t f(s clk ) t r(cmos) t f(cmos) typ. table 23 switching characteristics 1 (standard, one time prom version) table 24 switching characteristics 2 (standard, one time prom version)
56 single-chip 8-bit cmos microcomputer 3822 group mitsubishi microcomputers power source voltage a-d conversion reference voltage analog power source voltage analog input voltage an 0 Can 7 h input voltage p0 0 Cp0 7 , p1 0 Cp1 7 ,p3 4 Cp3 7 , p4 0 , p4 1 , p4 5 , p4 7 , p5 2 , p5 3, p5 6, p6 0 Cp6 7, p7 0 ,p7 1 (cm 4 = 0) h input voltage p2 0 Cp2 7 , p4 2 Cp4 4 ,p4 6 ,p5 0 , p5 1 , p5 4 , p5 5 , p5 7 h input voltage reset h input voltage x in l input voltage p0 0 Cp0 7 , p1 0 Cp1 7 ,p3 4 Cp3 7 , p4 0 , p4 1 , p4 5 , p4 7 , p5 2 , p5 3, p5 6, p6 0 Cp6 7, p7 0 ,p7 1 (cm 4 = 0) l input voltage p2 0 Cp2 7 , p4 2 Cp4 4 ,p4 6 ,p5 0 , p5 1 , p5 4 , p5 5 , p5 7 l input voltage reset l input voltage x in v o v o pd topr tstg C0.3 to 6.5 v power source voltage input voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 4 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 p6 0 Cp6 7 , p7 0 , p7 1 v cc v i symbol parameter conditions ratings unit all voltages are based on v ss . output transistors are cut off. v i v i v i v i v o v o v o input voltage v l1 input voltage v l2 input voltage v l3 input voltage reset, x in output voltage p0 0 Cp0 7 , p1 0 Cp1 7 output voltage p3 4 Cp3 7 output voltage p2 0 Cp2 7 , p4 1 Cp4 7 ,p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 , p7 1 output voltage seg 0 Cseg 11 output voltage x out power dissipation operating temperature storage temperature at output port at segment output at segment output C0.3 to v cc +0.3 C0.3 to v l2 v l1 to v l3 v l2 to v cc +0.3 C0.3 to v cc +0.3 C0.3 to v cc +0.3 C0.3 to v l3 C0.3 to v l3 C0.3 to v cc +0.3 C0.3 to v l3 C0.3 to v cc +0.3 300 C40 to 85 C65 to 150 v v v v v v v v v v v mw c c ta = 25c table 26 recommended operating conditions (extended operating temperature version) (v cc = 2.0 to 5.5 v, ta = C20 to 85 c, and v cc = 3.0 to 5.5 v, ta = C40 to C20c, unless otherwise noted) 5.5 5.5 5.5 5.5 5.5 v cc v cc v cc v cc v cc v cc 0.3 v cc 0.2 v cc 0.2 v cc 0.2 v cc v cc v ss v ref av ss v ia v ih v ih v ih v ih v il v il v il v il symbol parameter limits min. v v v v v v v v v v v v v unit 4.0 2.0 3.0 2.0 3.0 2.0 av ss 0.7v cc 0.8v cc 0.8v cc 0.8v cc 0 0 0 0 5.0 5.0 5.0 5.0 5.0 0 0 typ. max. power source voltage high-speed mode f(x in ) = 8 mhz middle-speed mode ta = C 20 to 85c f(x in ) = 8 mhz ta = C 40 to C 20c low-speed mode ta = C 20 to 85c ta = C 40 to C 20c table 25 absolute maximum ratings (extended operating temperature version)
57 single-chip 8-bit cmos microcomputer 3822 group mitsubishi microcomputers p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 (note 1) p4 1 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7, p7 0 , p7 1 (note 1) p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 (note 1) p4 1 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7, p7 0 , p7 1 (note 1) p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 (note 1) p4 1 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7, p7 0 , p7 1 (note 1) p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 (note 1) p4 1 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7, p7 0 , p7 1 (note 1) p0 0 Cp0 7 , p1 0 Cp1 7 (note 2) p2 0 Cp2 7 , p4 1 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7, p7 0 , p7 1 (note 2) p0 0 Cp0 7 , p1 0 Cp1 7 (note 2) p2 0 Cp2 7 , p4 1 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7, p7 0 , p7 1 (note 2) p0 0 Cp0 7 , p1 0 Cp1 7 (note 3) p2 0 Cp2 7 , p4 1 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7, p7 0 , p7 1 (note 3) p0 0 Cp0 7 , p1 0 Cp1 7 (note 3) p2 0 Cp2 7 , p4 1 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7, p7 0 , p7 1 (note 3) C40 C40 40 40 C20 C20 20 20 C2 C5 table 27 recommended operating conditions (extended operating temperature version) (v cc = 2.0 to 5.5 v, ta = C20 to 85 c, and v cc = 3.0 to 5.5 v, ta = C40 to C20 c, unless otherwise noted) notes 1: the total output current is the sum of all the currents flowing through all the applicable ports. the total average current is an average value mesured over 100 ms. the total peak current is the peak value of all the currents. 2: the peak output current is the peak current flowing in each port. 3: the average output current is an average value measured over 100 ms. 4: when the oscillation frequency has a duty cycle of 50 %. 5: when using the microcomputer in low-speed mode, make sure that the sub-clock input oscillation frequency on condition that f(x cin ) < f(x in )/3. h total peak output current h total peak output current l total peak output current l total peak output current h total average output current h total average output current l total average output current l total average output current h peak output current h peak output current i oh(peak) i oh(peak) i ol(peak) i ol(peak) i oh(avg) i oh(avg) i ol(avg) i ol(avg) i oh(peak) i oh(peak) symbol parameter limits min. ma ma ma ma ma ma ma ma ma ma unit typ. max. i ol(peak) i ol(peak) i oh(avg) i oh(avg) i ol(avg) 5 10 C1.0 C2.5 ma ma ma ma ma ma l peak output current l peak output current 2.5 5.0 4.0 v cc 8.0 2 ? v cc 8.0 50 h average output current h average output current l average output current l average output current input frequency for timers x and y (duty cycle 50%) i ol(avg) f(cntr 0 ) f(cntr 1 ) mhz mhz mhz mhz mhz khz (4.0 v v cc 5.5 v) (2.0 v v cc 4.0 v) 32.768 high-speed mode (4.0 v v cc 5.5 v) high-speed mode (2.0 v v cc 4.0 v) middle-speed mode main clock input oscillation frequency (note 4) sub-clock input oscillation frequency (notes 4, 5) f(x in ) f(x cin )
58 single-chip 8-bit cmos microcomputer 3822 group mitsubishi microcomputers table 28 electrical characteristics (extended operating temperature version) (v cc =2.0 to 5.5 v, ta = C20 to 85 c, and v cc = 3.0 to 5.5 v, ta = C40 to C20 c, unless otherwise noted) i ol = 10 ma i ol = 2.5 ma i ol = 2.5 ma v cc = 3.0 v i ol = 5 ma i ol = 1.25 ma i ol = 1.25 ma v cc = 3.0 v v ol i oh = C2.5 ma i oh = C0.6 ma v cc = 3.0 v i oh = C5 ma i oh = C1.25 ma i oh = C1.25 ma v cc = 3.0 v v v cc C2.0 h output voltage p0 0 Cp0 7 , p1 0 Cp1 7 symbol parameter limits min. unit 0.5 typ. max. test conditions v oh 2.0 0.5 reset : v cc = 2.0 v to 5.5 v v i = v cc pull-downs off v cc = 5 v, v i = v cc pull-downs on v cc = 3 v, v i = v cc pull-downs on v i = v cc h output voltage p2 0 Cp2 7 , p4 1 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 , p7 1 (note) l output voltage p0 0 Cp0 7 , p1 0 Cp1 7 l output voltage p2 0 Cp2 7 , p4 1 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 , p7 1 (note) hysteresis int 0 Cint 3 , adt, cntr 0, cntr 1, p2 0 Cp2 7 hysteresis s clk , r x d hysteresis reset h input current p0 0 Cp0 7 , p1 0 Cp1 7 , p3 4 Cp3 7 h input current p2 0 Cp2 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 , p7 1 (note) v oh v ol v t+ C v tC v t+ C v tC v t+ C v tC i ih i ih i ih v cc C2.0 v cc C0.5 30 6.0 C30 C6.0 0.5 0.5 70 2.0 0.5 55 170 5.0 5.0 C5.0 C5.0 C140 C45 v v v v v v v v v i ih i il v cc C0.9 v cc C0.9 v v v 1.1 v 1.1 5.0 a 25 v i = v cc v i = v cc v i = v ss v i = v ss pull-ups off v cc = 5 v, v i = v ss pull-ups on v cc = 3 v, v i = v ss pull-ups on v i = v ss v i = v ss h input current reset h input current x in l input current p0 0 Cp0 7 , p1 0 Cp1 7 , p3 4 Cp3 7 ,p4 0 l input current p2 0 Cp2 7 , p4 1 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 , p7 1 (note) l input current reset l input current x in 4.0 C5.0 C70 a a a a a a a a a a a i il i il i il C25 C4.0 note: when 1 is set to port x c switch bit (bit 4 at address 003b 16 ) of cpu mode register, the drive ability of port p7 0 is different from the value above men- tioned.
59 single-chip 8-bit cmos microcomputer 3822 group mitsubishi microcomputers table 29 electrical characteristics (extended operating temperature version) (v cc =2.0 to 5.5 v, ta = C20 to 85 c, and v cc = 3.0 to 5.5 v, ta = C40 to C20 c, unless otherwise noted) v 5.5 ? high-speed mode, v cc = 5 v f(x in ) = 8 mhz f(x cin ) = 32.768 khz output transistors off a-d converter in operating ? high-speed mode, v cc = 5 v f(x in ) = 8 mhz (in wit state) f(x cin ) = 32.768 khz output transistors off a-d converter stopped ? low-speed mode, v cc = 5 v, ta 55c f(x in ) = stopped f(x cin ) = 32.768 khz output transistors off ? low-speed mode, v cc = 5 v, ta = 25c f(x in ) = stopped f(x cin ) = 32.768 khz (in wit state) output transistors off ? low-speed mode, v cc = 3 v, ta 55c f(x in ) = stopped f(x cin ) = 32.768 khz output transistors off ? low-speed mode, v cc = 3 v, ta = 25c f(x in ) = stopped f(x cin ) = 32.768 khz (in wit state) output transistors off all oscillation stopped (in stp state) output transistors off symbol parameter limits min. unit typ. max. ta = 25 c ta = 85 c test conditions i cc power source current 6.4 v ram ram retention voltage at clock stop mode 2.0 1.6 25 7.0 15 4.5 0.1 3.2 36 14 22 9.0 1.0 10 ma a a a a a ma 13 table 30 a-d converter characteristics (extended operating temperature version) (v cc = 3.0 to 5.5 v, v ss =av ss = 0 v, ta = C40 to 85 c, 4 mhz f(x in ) 8 mhz, in middle/high-speed mode unless otherwise noted) symbol parameter limits min. unit typ. max. test conditions C resolution absolute accuracy (excluding quantization error) v cc = v ref = 4.0v to 5.5v f(x in ) = 8 mhz v cc = v ref = 3.0 v to 4.0v f(x in ) = 2 ? v cc mhz 12 bits lsb 8 2 note: when an internal trigger is used in middle-speed mode, it is 14 s. s f(x in ) = 8 mhz conversion time ladder resistor reference power source input current C t conv r ladder i vref k ? a analog port input current i ia a 35 150 v ref = 5 v 12.5 (note) 100 200 5.0 50
60 single-chip 8-bit cmos microcomputer 3822 group mitsubishi microcomputers table 31 timing requirements 1 (extended operating temperature version) (v cc = 4.0 to 5.5 v, v ss = 0 v, ta = C40 to 85 c, unless otherwise noted) 2 125 45 40 250 105 105 80 80 800 370 370 220 100 note: when bit 6 of address 001a 16 is 1 (clock synchronous). divide this value by four when bit 6 of address 001a 16 is 0 (uart). reset input l pulse width main clock input cycle time (x in input) main clock input h pulse width main clock input l pulse width cntr 0 , cntr 1 input cycle time cntr 0 , cntr 1 input h pulse width cntr 0 , cntr 1 input l pulse width int 0 to int 3 input h pulse width int 0 to int 3 input l pulse width serial i/o clock input cycle time (note) serial i/o clock input h pulse width (note) serial i/o clock input l pulse width (note) serial i/o input set up time serial i/o input hold time t w(reset) t c(x in ) t wh(x in ) t wl(x in ) t c(cntr) t wh(cntr) t wl(cntr) t wh(int) t wl(int) t c(s clk ) t wh(s clk ) t wl(s clk ) t su(r x dCs clk ) t h(s clk Cr x d) symbol parameter limits min. s ns ns ns ns ns ns ns ns ns ns ns ns ns unit typ. max. table 32 timing requirements 2 (extended operating temperature version) (v cc = 2.0 to 4.0 v, v ss = 0 v, ta = C20 to 85 c, and v cc = 3.0 to 4.0 v, ta = C40 to C20 c, unless otherwise noted) 2 125 45 40 900/(v cc C0.4) 450/(v cc C0.4)C20 450/(v cc C0.4)C20 230 230 2000 950 950 400 200 reset input l pulse width main clock input cycle time (x in input) main clock input h pulse width main clock input l pulse width cntr 0 , cntr 1 input cycle time cntr 0 , cntr 1 input h pulse width cntr 0 , cntr 1 input l pulse width int 0 to int 3 input h pulse width int 0 to int 3 input l pulse width serial i/o clock input cycle time (note) serial i/o clock input h pulse width (note) serial i/o clock input l pulse width (note) serial i/o input set up time serial i/o input hold time t w(reset) t c(x in ) t wh(x in ) t wl(x in ) t c(cntr) t wh(cntr) t wl(cntr) t wh(int) t wl(int) t c(s clk ) t wh(s clk ) t wl(s clk ) t su(r x dCs clk ) t h(s clk Cr x d) symbol parameter limits min. s ns ns ns ns ns ns ns ns ns ns ns ns ns unit max. note: when bit 6 of address 001a 16 is 1 (clock synchronous). divide this value by four when bit 6 of address 001a 16 is 0 (uart). typ.
61 single-chip 8-bit cmos microcomputer 3822 group mitsubishi microcomputers table 33 switching characteristics 1 (extended operating temperature version) (v cc = 4.0 to 5.5 v, v ss = 0 v, ta = C40 to 85 c, unless otherwise noted) notes 1: when the p4 5 /t x d p-channel output disable bit of the uart control register (bit 4 of address 001b 16 ) is 0. 2: x out and x cout pins are excluded. serial i/o clock output h pulse width serial i/o clock output l pulse width serial i/o output delay time (note 1) serial i/o output valid time (note 1) serial i/o clock output rising time serial i/o clock output falling time cmos output rising time (note 2) cmos output falling time (note 2) 140 30 30 30 30 symbol parameter limits min. ns ns ns ns ns ns ns ns unit t c (s clk )/2C30 t c (s clk )/2C30 C30 10 10 typ. max. t wh(s clk ) t wl(s clk ) t d(s clk Ct x d) t v(s clk Ct x d) t r(s clk ) t f(s clk ) t r(cmos) t f(cmos) table 34 switching characteristics 2 (extended operating temperature version) (v cc = 2.0 to 4.0 v, v ss = 0 v, ta = C20 to 85 c, and v cc = 3.0 to 4.0 v, v ss = 0 v, ta = C40 to C20 c, unless otherwise noted) ns ns ns ns ns ns ns ns unit notes 1: when the p4 5 /t x d p-channel output disable bit of the uart control register (bit 4 of address 001b 16 ) is 0. 2: x out and x cout pins are excluded. serial i/o clock output h pulse width serial i/o clock output l pulse width serial i/o output delay time (note 1) serial i/o output valid time (note 1) serial i/o clock output rising time serial i/o clock output falling time cmos output rising time (note 2) cmos output falling time (note 2) 350 50 50 50 50 symbol parameter limits min. t c (s clk )/2C50 t c (s clk )/2C50 C30 20 20 max. t wh(s clk ) twl(s clk ) t d(s clk Ct x d) t v(s clk Ct x d) t r(s clk ) t f(s clk ) t r(cmos) t f(cmos) typ.
62 single-chip 8-bit cmos microcomputer 3822 group mitsubishi microcomputers v o v o pd topr tstg C0.3 to 7.0 v power source voltage input voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 4 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 p6 0 Cp6 7 , p7 0 , p7 1 v cc v i symbol parameter conditions ratings unit all voltages are based on v ss . output transistors are cut off. v i v i v i v i v o v o v o input voltage v l1 input voltage v l2 input voltage v l3 input voltage reset, x in output voltage p0 0 Cp0 7 , p1 0 Cp1 7 output voltage p3 4 Cp3 7 output voltage p2 0 Cp2 7 , p4 1 Cp4 7 ,p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 , p7 1 output voltage seg 0 Cseg 11 output voltage x out power dissipation operating temperature storage temperature at output port at segment output at segment output C0.3 to v cc +0.3 C0.3 to v l2 v l1 to v l3 v l2 to v cc +0.3 C0.3 to v cc +0.3 C0.3 to v cc +0.3 C0.3 to v l3 +0.3 C0.3 to v l3 +0.3 C0.3 to v cc +0.3 C0.3 to v l3 +0.3 C0.3 to v cc +0.3 300 C20 to 85 C40 to 150 v v v v v v v v v v v mw c c ta = 25c (v cc = 2.2 to 5.5 v, ta = C20 to 85 c, unless otherwise noted) power source voltage a-d conversion reference voltage analog power source voltage analog input voltage an 0 Can 7 5.5 5.5 5.5 v cc v cc v cc v ss v ref av ss v ia symbol parameter limits min. v v v v v unit 4.0 2.2 2.2 2.0 av ss 5.0 5.0 5.0 0 0 typ. max. power source voltage high-speed mode f(x in ) = 8 mhz middle-speed mode f(x in ) = 8 mhz low-speed mode table 35 absolute maximum ratings (m version) table 36 recommended operating conditions (m version)
63 single-chip 8-bit cmos microcomputer 3822 group mitsubishi microcomputers (v cc = 2.5 to 5.5 v, ta = C20 to 85 c, unless otherwise noted) h input voltage p0 0 Cp0 7 , p1 0 Cp1 7 ,p3 4 Cp3 7 , p4 0 , p4 1 , p4 5 , p4 7 , p5 2 , p5 3, p5 6, p6 0 Cp6 7, p7 0 ,p7 1 (cm 4 = 0) h input voltage p2 0 Cp2 7 , p4 2 Cp4 4 ,p4 6 ,p5 0 , p5 1 , p5 4 , p5 5 , p5 7 h input voltage reset h input voltage x in l input voltage p0 0 Cp0 7 , p1 0 Cp1 7 ,p3 4 Cp3 7 , p4 0 , p4 1 , p4 5 , p4 7 , p5 2 , p5 3, p5 6, p6 0 Cp6 7, p7 0 ,p7 1 (cm 4 = 0) l input voltage p2 0 Cp2 7 , p4 2 Cp4 4 ,p4 6 ,p5 0 , p5 1 , p5 4 , p5 5 , p5 7 l input voltage reset l input voltage x in v cc v cc v cc v cc 0.3 v cc 0.2 v cc 0.2 v cc 0.2 v cc v ih v ih v ih v ih v il v il v il v il symbol parameter limits min. v v v v v v v v unit 0.7v cc 0.8v cc 0.8v cc 0.8v cc 0 0 0 0 typ. max. (v cc = 2.2 to 5.5 v, ta = C20 to 85 c, unless otherwise noted) h input voltage p0 0 Cp0 7 , p1 0 Cp1 7 ,p3 4 Cp3 7 , p4 0 , p4 1 , p4 5 , p4 7 , p5 2 , p5 3, p5 6, p6 0 Cp6 7, p7 0 ,p7 1 (cm 4 = 0) h input voltage p2 0 Cp2 7 , p4 2 Cp4 4 ,p4 6 ,p5 0 , p5 1 , p5 4 , p5 5 , p5 7 h input voltage reset h input voltage x in l input voltage p0 0 Cp0 7 , p1 0 Cp1 7 ,p3 4 Cp3 7 , p4 0 , p4 1 , p4 5 , p4 7 , p5 2 , p5 3, p5 6, p6 0 Cp6 7, p7 0 ,p7 1 (cm 4 = 0) l input voltage p2 0 Cp2 7 , p4 2 Cp4 4 ,p4 6 ,p5 0 , p5 1 , p5 4 , p5 5 , p5 7 l input voltage reset l input voltage x in v cc v cc v cc v cc 0.2 v cc 0.05 v cc 0.05 v cc 0.05 v cc v ih v ih v ih v ih v il v il v il v il symbol parameter limits min. v v v v v v v v unit 0.8v cc 0.95v cc 0.95v cc 0.95v cc 0 0 0 0 typ. max. table 37 recommended operating conditions (m version) table 38 recommended operating conditions (m version)
64 single-chip 8-bit cmos microcomputer 3822 group mitsubishi microcomputers p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 (note 1) p4 1 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7, p7 0 , p7 1 (note 1) p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 (note 1) p4 1 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7, p7 0 , p7 1 (note 1) p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 (note 1) p4 1 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7, p7 0 , p7 1 (note 1) p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 (note 1) p4 1 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7, p7 0 , p7 1 (note 1) p0 0 Cp0 7 , p1 0 Cp1 7 (note 2) p2 0 Cp2 7 , p4 1 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7, p7 0 , p7 1 (note 2) p0 0 Cp0 7 , p1 0 Cp1 7 (note 2) p2 0 Cp2 7 , p4 1 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7, p7 0 , p7 1 (note 2) p0 0 Cp0 7 , p1 0 Cp1 7 (note 3) p2 0 Cp2 7 , p4 1 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7, p7 0 , p7 1 (note 3) p0 0 Cp0 7 , p1 0 Cp1 7 (note 3) p2 0 Cp2 7 , p4 1 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7, p7 0 , p7 1 (note 3) C40 C40 40 40 C20 C20 20 20 C2 C5 (v cc = 2.2 to 5.5 v, ta = C20 to 85 c, unless otherwise noted) notes 1: the total output current is the sum of all the currents flowing through all the applicable ports. the total average current is an average value measured over 100 ms. the total peak current is the peak value of all the currents. 2: the peak output current is the peak current flowing in each port. 3: the average output current is an average value measured over 100 ms. 4: when the oscillation frequency has a duty cycle of 50%. 5: when using the microcomputer in low-speed mode, make sure that the sub-clock input oscillation frequency on condition that f(x cin ) < f(x in )/3. h total peak output current h total peak output current l total peak output current l total peak output current h total average output current h total average output current l total average output current l total average output current h peak output current h peak output current i oh(peak) i oh(peak) i ol(peak) i ol(peak) i oh(avg) i oh(avg) i ol(avg) i ol(avg) i oh(peak) i oh(peak) symbol parameter limits min. ma ma ma ma ma ma ma ma ma ma unit typ. max. i ol(peak) i ol(peak) i oh(avg) i oh(avg) i ol(avg) 5 10 C1.0 C2.5 ma ma ma ma ma ma l peak output current l peak output current h average output current h average output current l average output current l average output current input frequency for timers x and y (duty cycle 50%) i ol(avg) f(cntr 0 ) f(cntr 1 ) mhz mhz mhz mhz mhz khz (4.0 v v cc 5.5 v) (2.2 v v cc 4.0 v) 32.768 high-speed mode (4.0 v v cc 5.5 v) high-speed mode (2.2 v v cc 4.0 v) middle-speed mode main clock input oscillation frequency (note 4) sub-clock input oscillation frequency (notes 4, 5) f(x in ) f(x cin ) 2.5 5.0 4.0 (10 ? v cc -4)/9 8.0 (20 ? v cc -8)/9 8.0 50 table 39 recommended operating conditions (m version)
65 single-chip 8-bit cmos microcomputer 3822 group mitsubishi microcomputers i ol = 10 ma i ol = 2.5 ma i ol = 2.5 ma v cc = 2.5 v i ol = 5 ma i ol = 1.25 ma i ol = 1.25 ma v cc = 2.5 v v ol i oh = C2.5 ma i oh = C0.6 ma v cc = 2.5 v i oh = C5 ma i oh = C1.25 ma i oh = C1.25 ma v cc = 2.5 v v v cc C2.0 h output voltage p0 0 Cp0 7 , p1 0 Cp1 7 symbol parameter limits min. unit 0.5 typ. max. test conditions v oh 2.0 0.5 (v cc = 4.0 to 5.5 v, ta = C20 to 85 c, unless otherwise noted) reset : v cc = 2.2 v to 5.5 v v i = v cc pull-downs off v cc = 5 v, v i = v cc pull-downs on v cc = 3 v, v i = v cc pull-downs on v i = v cc h output voltage p2 0 Cp2 7 , p4 1 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 , p7 1 (note) l output voltage p0 0 Cp0 7 , p1 0 Cp 7 l output voltage p2 0 Cp2 7 , p4 1 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 , p7 1 (note) hysteresis int 0 Cint 3 , adt, cntr 0, cntr 1, p2 0 Cp2 7 hysteresis s clk , r x d hysteresis reset h input current p0 0 Cp0 7 , p1 0 Cp1 7 , p3 4 Cp3 7 h input current p2 0 Cp2 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 , p7 1 (note) v oh v ol v t+ C v tC v t+ C v tC v t+ C v tC i ih i ih i ih v cc C2.0 v cc C0.5 30 6.0 C30 C6.0 0.5 0.5 70 2.0 0.5 45 140 5.0 5.0 C5.0 C5.0 C140 C45 v v v v v v v v v i ih i il v cc C1.0 v cc C1.0 v v v 1.0 v 1.0 5.0 a 25 v i = v cc v i = v cc v i = v ss v i = v ss pull-ups off v cc = 5 v, v i = v ss pull-ups on v cc = 3 v, v i = v ss pull-ups on v i = v ss v i = v ss h input current reset h input current x in l input current p0 0 Cp0 7 , p1 0 Cp1 7 , p3 4 Cp3 7 ,p4 0 l input current p2 0 Cp2 7 , p4 1 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 , p7 1 (note) l input current reset l input current x in 4.0 C5.0 C70 a a a a a a a a a a a i il i il i il C25 C4.0 note: when 1 is set to the port x c switch bit (bit 4 at address 003b 16 ) of cpu mode register, the drive ability of port p7 0 is different from the value above mentioned. table 40 electrical characteristics (m version)
66 single-chip 8-bit cmos microcomputer 3822 group mitsubishi microcomputers (v cc = 2.2 to 5.5 v, ta = C20 to 85 c, unless otherwise noted) v 5.5 ? high-speed mode, v cc = 5 v f(x in ) = 8 mhz f(x cin ) = 32.768 khz output transistors off a-d converter in operating ? high-speed mode, v cc = 5 v f(x in ) = 8 mhz (in wit state) f(x cin ) = 32.768 khz output transistors off a-d converter stopped ? low-speed mode, v cc = 5 v, ta 55c f(x in ) = stopped f(x cin ) = 32.768 khz output transistors off ? low-speed mode, v cc = 5 v, ta = 25c f(x in ) = stopped f(x cin ) = 32.768 khz (in wit state) output transistors off ? low-speed mode, v cc = 3 v, ta 55c f(x in ) = stopped f(x cin ) = 32.768 khz output transistors off ? low-speed mode, v cc = 3 v, ta = 25c f(x in ) = stopped f(x cin ) = 32.768 khz (in wit state) output transistors off all oscillation stopped (in stp state) output transistors off symbol parameter limits min. unit typ. max. ta = 25 c ta = 85 c test conditions i cc power source current 6.4 v ram ram retention voltage at clock stop mode 2.0 1.6 25 7.0 15 4.5 0.1 3.2 36 14 22 9.0 1.0 10 ma a a a a a ma 13 (v cc = 4.0 to 5.5 v, v ss = 0 v, ta = C20 to 85 c, 4 mhz f(x in ) 8 mhz, in middle/high-speed mode, unless otherwise noted) table 41 electrical characteristics (m version) table 42 a-d converter characteristics (m version) symbol parameter limits min. unit typ. max. test conditions C resolution absolute accuracy (excluding quantization error) v cc = v ref = 5v f(x in ) = 8 mhz v ref = 5 v 12 bits lsb 35 150 8 2 note: when an internal trigger is used in middle-speed mode, it is 14 s. s conversion time ladder resistor reference power source input current C t conv r ladder i vref k ? a analog port input current i ia a 12.5 (note) 100 200 5.0 50
67 single-chip 8-bit cmos microcomputer 3822 group mitsubishi microcomputers (v cc = 4.0 to 5.5 v, v ss = 0 v, ta = C20 to 85 c, unless otherwise noted) 2 125 45 40 250 105 105 80 80 800 370 370 220 100 note: when bit 6 of address 001a 16 is 1 (clock synchronous). divide this value by four when bit 6 of address 001a 16 is 0 (uart). reset input l pulse width main clock input cycle time (x in input) main clock input h pulse width main clock input l pulse width cntr 0 , cntr 1 input cycle time cntr 0 , cntr 1 input h pulse width cntr 0 , cntr 1 input l pulse width int 0 to int 3 input h pulse width int 0 to int 3 input l pulse width serial i/o clock input cycle time (note) serial i/o clock input h pulse width (note) serial i/o clock input l pulse width (note) serial i/o input set up time serial i/o input hold time t w(reset) t c(x in ) t wh(x in ) t wl(x in ) t c(cntr) t wh(cntr) t wl(cntr) t wh(int) t wl(int) t c(s clk ) t wh(s clk ) t wl(s clk ) t su(r x dCs clk ) t h(s clk Cr x d) symbol parameter limits min. s ns ns ns ns ns ns ns ns ns ns ns ns ns unit typ. max. (v cc = 2.2 to 4.0 v, v ss = 0 v, ta = C20 to 85 c, unless otherwise noted) 2 125 45 40 900/(v cc C0.4) 450/(v cc C0.4)C20 450/(v cc C0.4)C20 230 230 2000 950 950 400 200 reset input l pulse width main clock input cycle time (x in input) main clock input h pulse width main clock input l pulse width cntr 0 , cntr 1 input cycle time cntr 0 , cntr 1 input h pulse width cntr 0 , cntr 1 input l pulse width int 0 to int 3 input h pulse width int 0 to int 3 input l pulse width serial i/o clock input cycle time (note) serial i/o clock input h pulse width (note) serial i/o clock input l pulse width (note) serial i/o input set up time serial i/o input hold time t w(reset) t c(x in ) t wh(x in ) t wl(x in ) t c(cntr) t wh(cntr) t wl(cntr) t wh(int) t wl(int) t c(s clk ) t wh(s clk ) t wl(s clk ) t su(r x dCs clk ) t h(s clk Cr x d) symbol parameter limits min. s ns ns ns ns ns ns ns ns ns ns ns ns ns unit typ. max. note: when bit 6 of address 001a 16 is 1 (clock synchronous). divide this value by four when bit 6 of address 001a 16 is 0 (uart). table 43 timing requirements 1 (m version) table 44 timing requirements 2 (m version)
68 single-chip 8-bit cmos microcomputer 3822 group mitsubishi microcomputers (v cc = 4.0 to 5.5 v, v ss = 0 v, ta = C20 to 85 c, unless otherwise noted) notes 1: when the p4 5 /t x d p-channel output disable bit of the uart control register (bit 4 of address 001b 16 ) is 0. 2: x out and x cout pins are excluded. serial i/o clock output h pulse width serial i/o clock output l pulse width serial i/o output delay time (note 1) serial i/o output valid time (note 1) serial i/o clock output rising time serial i/o clock output falling time cmos output rising time (note 2) cmos output falling time (note 2) 140 30 30 30 30 symbol parameter limits min. ns ns ns ns ns ns ns ns unit t c (s clk )/2C30 t c (s clk )/2C30 C30 10 10 typ. max. t wh(s clk ) t wl(s clk ) t d(s clk Ct x d) t v(s clk Ct x d) t r(s clk ) t f(s clk ) t r(cmos) t f(cmos) (v cc = 2.2 to 4.0 v, v ss = 0 v, ta = C20 to 85 c, unless otherwise noted) ns ns ns ns ns ns ns ns unit notes 1: when the p4 5 /t x d p-channel output disable bit of the uart control register (bit 4 of address 001b 16 ) is 0. 2: x out and x cout pins are excluded. serial i/o clock output h pulse width serial i/o clock output l pulse width serial i/o output delay time (note 1) serial i/o output valid time (note 1) serial i/o clock output rising time serial i/o clock output falling time cmos output rising time (note 2) cmos output falling time (note 2) 350 50 50 50 50 symbol parameter limits min. t c (s clk )/2C50 t c (s clk )/2C50 C30 20 20 max. t wh(s clk ) twl(s clk ) t d(s clk Ct x d) t v(s clk Ct x d) t r(s clk ) t f(s clk ) t r(cmos) t f(cmos) typ. table 45 switching characteristics 1 (m version) table 46 switching characteristics 2 (m version)
69 single-chip 8-bit cmos microcomputer 3822 group mitsubishi microcomputers v o v o pd topr tstg C0.3 to 6.5 v power source voltage input voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 4 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 p6 0 Cp6 7 , p7 0 , p7 1 v cc v i symbol parameter conditions ratings unit all voltages are based on v ss . output transistors are cut off. v i v i v i v i v o v o v o input voltage v l1 input voltage v l2 input voltage v l3 input voltage reset, x in output voltage p0 0 Cp0 7 , p1 0 Cp1 7 output voltage p3 4 Cp3 7 output voltage p2 0 Cp2 7 , p4 1 Cp4 7 ,p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 , p7 1 output voltage seg 0 Cseg 11 output voltage x out power dissipation operating temperature storage temperature at output port at segment output at segment output C0.3 to v cc +0.3 C0.3 to v l2 v l1 to v l3 v l2 to v cc +0.3 C0.3 to v cc +0.3 C0.3 to v cc +0.3 C0.3 to v l3 C0.3 to v l3 C0.3 to v cc +0.3 C0.3 to v l3 C0.3 to v cc +0.3 300 C20 to 85 C40 to 150 v v v v v v v v v v v mw c c ta = 25c (v cc = 2.0 to 5.5 v, ta = C20 to 85 c, unless otherwise noted) power source voltage a-d conversion reference voltage analog power source voltage analog input voltage an 0 Can 7 h input voltage p0 0 Cp0 7 , p1 0 Cp1 7 ,p3 4 Cp3 7 , p4 0 , p4 1 , p4 5 , p4 7 , p5 2 , p5 3, p5 6, p6 0 Cp6 7, p7 0 ,p7 1 (cm 4 = 0) h input voltage p2 0 Cp2 7 , p4 2 Cp4 4 ,p4 6 ,p5 0 , p5 1 , p5 4 , p5 5 , p5 7 h input voltage reset h input voltage x in l input voltage p0 0 Cp0 7 , p1 0 Cp1 7 ,p3 4 Cp3 7 , p4 0 , p4 1 , p4 5 , p4 7 , p5 2 , p5 3, p5 6, p6 0 Cp6 7, p7 0 ,p7 1 (cm 4 = 0) l input voltage p2 0 Cp2 7 , p4 2 Cp4 4 ,p4 6 ,p5 0 , p5 1 , p5 4 , p5 5 , p5 7 l input voltage reset l input voltage x in 5.5 5.5 5.5 v cc v cc v cc v cc v cc v cc 0.3 v cc 0.2 v cc 0.2 v cc 0.2 v cc v cc v ss v ref av ss v ia v ih v ih v ih v ih v il v il v il v il symbol parameter limits min. v v v v v v v v v v v v v unit 4.0 2.0 2.0 2.0 av ss 0.7v cc 0.8v cc 0.8v cc 0.8v cc 0 0 0 0 5.0 5.0 5.0 0 0 typ. max. power source voltage high-speed mode f(x in ) = 8 mhz middle-speed mode f(x in ) = 8 mhz low-speed mode table 47 absolute maximum ratings (h version) table 48 recommended operating conditions (h version)
70 single-chip 8-bit cmos microcomputer 3822 group mitsubishi microcomputers p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 (note 1) p4 1 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7, p7 0 , p7 1 (note 1) p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 (note 1) p4 1 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7, p7 0 , p7 1 (note 1) p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 (note 1) p4 1 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7, p7 0 , p7 1 (note 1) p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 (note 1) p4 1 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7, p7 0 , p7 1 (note 1) p0 0 Cp0 7 , p1 0 Cp1 7 (note 2) p2 0 Cp2 7 , p4 1 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7, p7 0 , p7 1 (note 2) p0 0 Cp0 7 , p1 0 Cp1 7 (note 2) p2 0 Cp2 7 , p4 1 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7, p7 0 , p7 1 (note 2) p0 0 Cp0 7 , p1 0 Cp1 7 (note 3) p2 0 Cp2 7 , p4 1 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7, p7 0 , p7 1 (note 3) p0 0 Cp0 7 , p1 0 Cp1 7 (note 3) p2 0 Cp2 7 , p4 1 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7, p7 0 , p7 1 (note 3) C40 C40 40 40 C20 C20 20 20 C2 C5 (v cc = 2.0 to 5.5 v, ta = C20 to 85c, unless otherwise noted) notes 1: the total output current is the sum of all the currents flowing through all the applicable ports. the total average current is an average value measured over 100 ms. the total peak current is the peak value of all the currents. 2: the peak output current is the peak current flowing in each port. 3: the average output current is an average value measured over 100 ms. 4: when the oscillation frequency has a duty cycle of 50 %. 5: when using the microcomputer in low-speed mode, make sure that the sub-clock input oscillation frequency on condition that f(x cin ) < f(x in )/3. h total peak output current h total peak output current l total peak output current l total peak output current h total average output current h total average output current l total average output current l total average output current h peak output current h peak output current i oh(peak) i oh(peak) i ol(peak) i ol(peak) i oh(avg) i oh(avg) i ol(avg) i ol(avg) i oh(peak) i oh(peak) symbol parameter limits min. ma ma ma ma ma ma ma ma ma ma unit typ. max. i ol(peak) i ol(peak) i oh(avg) i oh(avg) i ol(avg) 5 10 C1.0 C2.5 ma ma ma ma ma ma l peak output current l peak output current 2.5 5.0 4.0 v cc 8.0 2 ? v cc 8.0 50 h average output current h average output current l average output current l average output current input frequency for timers x and y (duty cycle 50%) i ol(avg) f(cntr 0 ) f(cntr 1 ) mhz mhz mhz mhz mhz khz (4.0 v v cc 5.5 v) (2.0 v v cc 4.0 v) 32.768 high-speed mode (4.0 v v cc 5.5 v) high-speed mode (2.0 v v cc 4.0 v) middle-speed mode main clock input oscillation frequency (note 4) sub-clock input oscillation frequency (notes 4, 5) f(x in ) f(x cin ) table 49 recommended operating conditions (h version)
71 single-chip 8-bit cmos microcomputer 3822 group mitsubishi microcomputers i ol = 10 ma i ol = 2.5 ma i ol = 2.5 ma v cc = 2.5 v i ol = 5 ma i ol = 1.25 ma i ol = 1.25 ma v cc = 2.5 v v ol i oh = C2.5 ma i oh = C0.6 ma v cc = 2.5 v i oh = C5 ma i oh = C1.25 ma i oh = C1.25 ma v cc = 2.5 v v v cc C2.0 h output voltage p0 0 Cp0 7 , p1 0 Cp1 7 symbol parameter limits min. unit 0.5 typ. max. test conditions v oh 2.0 0.5 (v cc = 4.0 to 5.5 v, ta = C20 to 85 c, unless otherwise noted) reset : v cc = 2.0 v to 5.5 v v i = v cc pull-downs off v cc = 5 v, v i = v cc pull-downs on v cc = 3 v, v i = v cc pull-downs on v i = v cc h output voltage p2 0 Cp2 7 , p4 1 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 , p7 1 (note) l output voltage p0 0 Cp0 7 , p1 0 Cp 7 l output voltage p2 0 Cp2 7 , p4 1 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 , p7 1 (note) hysteresis int 0 Cint 3 , adt, cntr 0, cntr 1, p2 0 Cp2 7 hysteresis s clk , r x d hysteresis reset h input current p0 0 Cp0 7 , p1 0 Cp1 7 , p3 4 Cp3 7 h input current p2 0 Cp2 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 , p7 1 (note) v oh v ol v t+ C v tC v t+ C v tC v t+ C v tC i ih i ih i ih v cc C2.0 v cc C0.5 30 6.0 C30 C6.0 0.5 0.5 70 2.0 0.5 45 140 5.0 5.0 C5.0 C5.0 C140 C45 v v v v v v v v v i ih i il v cc C1.0 v cc C1.0 v v v 1.0 v 1.0 5.0 a 25 v i = v cc v i = v cc v i = v ss v i = v ss pull-ups off v cc = 5 v, v i = v ss pull-ups on v cc = 3 v, v i = v ss pull-ups on v i = v ss v i = v ss h input current reset h input current x in l input current p0 0 Cp0 7 , p1 0 Cp1 7 , p3 4 Cp3 7 ,p4 0 l input current p2 0 Cp2 7 , p4 1 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 , p7 1 (note) l input current reset l input current x in 4.0 5.0 C70 a a a a a a a a a a a i il i il i il C25 C4.0 note: when 1 is set to the port x c switch bit (bit 4 at address 003b 16 ) of cpu mode register, the drive ability of port p7 0 is different from the value above mentioned. table 50 electrical characteristics (h version)
72 single-chip 8-bit cmos microcomputer 3822 group mitsubishi microcomputers (v cc =2.0 to 5.5 v, ta = C20 to 85 c, unless otherwise noted) v 5.5 ? high-speed mode, v cc = 5 v f(x in ) = 8 mhz f(x cin ) = 32.768 khz output transistors off a-d converter in operating ? high-speed mode, v cc = 5 v f(x in ) = 8 mhz (in wit state) f(x cin ) = 32.768 khz output transistors off a-d converter stopped ? low-speed mode, v cc = 5 v, ta 55c f(x in ) = stopped f(x cin ) = 32.768 khz output transistors off ? low-speed mode, v cc = 5 v, ta = 25c f(x in ) = stopped f(x cin ) = 32.768 khz (in wit state) output transistors off ? low-speed mode, v cc = 3 v, ta 55c f(x in ) = stopped f(x cin ) = 32.768 khz output transistors off ? low-speed mode, v cc = 3 v, ta = 25c f(x in ) = stopped f(x cin ) = 32.768 khz (in wit state) output transistors off all oscillation stopped (in stp state) output transistors off symbol parameter limits min. unit typ. max. ta = 25 c ta = 85 c test conditions i cc power source current 6.4 v ram ram retention voltage at clock stop mode 2.0 1.6 25 7.0 15 4.5 0.1 3.2 36 14 22 9.0 1.0 10 ma a a a a a ma 13 (v cc = 2.2 to 5.5 v, v ss = av ss = 0 v, ta = C20 to 85 c, 4 mhz f(x in ) 8 mhz, in middle/high-speed mode unless otherwise noted) symbol parameter limits min. unit typ. max. test conditions C resolution absolute accuracy (excluding quantization error) v cc = v ref = 4.0 v to 5.5 v f(x in ) = 8 mhz v cc = v ref = 2.2 v to 4.0v f(x in ) = 2 ? v cc mhz 12 bits lsb 8 2 note: when an internal trigger is used in middle-speed mode, it is 14 s. s f(x in ) = 8 mhz conversion time ladder resistor reference power source input current C t conv r ladder i vref k ? a analog port input current i ia a 35 150 v ref = 5 v 12.5 (note) 100 200 5.0 50 table 51 electrical characteristics (h version) table 52 a-d converter characteristics (h version)
73 single-chip 8-bit cmos microcomputer 3822 group mitsubishi microcomputers (v cc = 4.0 to 5.5 v, v ss = 0 v, ta = C20 to 85 c, unless otherwise noted) 2 125 45 40 250 105 105 80 80 800 370 370 220 100 note: when bit 6 of address 001a 16 is 1 (clock synchronous). divide this value by four when bit 6 of address 001a 16 is 0 (uart). reset input l pulse width main clock input cycle time (x in input) main clock input h pulse width main clock input l pulse width cntr 0 , cntr 1 input cycle time cntr 0 , cntr 1 input h pulse width cntr 0 , cntr 1 input l pulse width int 0 to int 3 input h pulse width int 0 to int 3 input l pulse width serial i/o clock input cycle time (note) serial i/o clock input h pulse width (note) serial i/o clock input l pulse width (note) serial i/o input set up time serial i/o input hold time t w(reset) t c(x in ) t wh(x in ) t wl(x in ) t c(cntr) t wh(cntr) t wl(cntr) t wh(int) t wl(int) t c(s clk ) t wh(s clk ) t wl(s clk ) t su(r x dCs clk ) t h(s clk Cr x d) symbol parameter limits min. s ns ns ns ns ns ns ns ns ns ns ns ns ns unit typ. max. (v cc = 2.0 to 4.0 v, v ss = 0 v, ta = C20 to 85 c, unless otherwise noted) 2 125 45 40 900/(v cc C0.4) 450/(v cc C0.4)C20 450/(v cc C0.4)C20 230 230 2000 950 950 400 200 reset input l pulse width main clock input cycle time (x in input) main clock input h pulse width main clock input l pulse width cntr 0 , cntr 1 input cycle time cntr 0 , cntr 1 input h pulse width cntr 0 , cntr 1 input l pulse width int 0 to int 3 input h pulse width int 0 to int 3 input l pulse width serial i/o clock input cycle time (note) serial i/o clock input h pulse width (note) serial i/o clock input l pulse width (note) serial i/o input set up time serial i/o input hold time t w(reset) t c(x in ) t wh(x in ) t wl(x in ) t c(cntr) t wh(cntr) t wl(cntr) t wh(int) t wl(int) t c(s clk ) t wh(s clk ) t wl(s clk ) t su(r x dCs clk ) t h(s clk Cr x d) symbol parameter limits min. s ns ns ns ns ns ns ns ns ns ns ns ns ns unit typ. max. note: when bit 6 of address 001a 16 is 1 (clock synchronous). divide this value by four when bit 6 of address 001a 16 is 0 (uart). table 53 timing requirements 1 (h version) table 54 timing requirements 2 (h version)
74 single-chip 8-bit cmos microcomputer 3822 group mitsubishi microcomputers (v cc = 4.0 to 5.5 v, v ss = 0 v, ta = C20 to 85 c, unless otherwise noted) notes1: when the p4 5 /t x d p-channel output disable bit of the uart control register (bit 4 of address 001b 16 ) is 0. 2: x out and x cout pins are excluded. serial i/o clock output h pulse width serial i/o clock output l pulse width serial i/o output delay time (note 1) serial i/o output valid time (note 1) serial i/o clock output rising time serial i/o clock output falling time cmos output rising time (note 2) cmos output falling time (note 2) 140 30 30 30 30 symbol parameter limits min. ns ns ns ns ns ns ns ns unit t c (s clk )/2C30 t c (s clk )/2C30 C30 10 10 typ. max. t wh(s clk ) t wl(s clk ) t d(s clk Ct x d) t v(s clk Ct x d) t r(s clk ) t f(s clk ) t r(cmos) t f(cmos) (v cc = 2.0 to 4.0 v, v ss = 0 v, ta = C20 to 85 c, unless otherwise noted) ns ns ns ns ns ns ns ns unit notes1: when the p4 5 /t x d p-channel output disable bit of the uart control register (bit 4 of address 001b 16 ) is 0. 2: x out and x cout pins are excluded. serial i/o clock output h pulse width serial i/o clock output l pulse width serial i/o output delay time (note 1) serial i/o output valid time (note 1) serial i/o clock output rising time serial i/o clock output falling time cmos output rising time (note 2) cmos output falling time (note 2) 350 50 50 50 50 symbol parameter limits min. t c (s clk )/2C50 t c (s clk )/2C50 C30 20 20 max. t wh(s clk ) twl(s clk ) t d(s clk Ct x d) t v(s clk Ct x d) t r(s clk ) t f(s clk ) t r(cmos) t f(cmos) typ. fig. 52 circuit for measuring output switching characteristics table 55 switching characteristics 1 (h version) table 56 switching characteristics 2 (h version) m e a s u r e m e n t o u t p u t p i n 1 0 0 p f c m o s o u t p u t n ote: wh en bi t 4 o f t h e uart contro l reg i ster (address 001b 16 ) is 1 . (n-channel open- drain output mode) n -c h anne l open- d ra i n output (n ote ) 1 k ?
75 single-chip 8-bit cmos microcomputer 3822 group mitsubishi microcomputers fig. 53 timing diagram t w(reset) 0.8 v c c 0.2 v cc r e s e t t c(x in ) t c ( c n t r ) t w h ( c n t r ) t w l ( c n t r ) 0 . 8 v c c 0.2 v c c c n t r 0 , c n t r 1 t w h ( i n t ) t w l ( i n t ) 0 . 8 v c c 0.2 v c c i n t 0 C i n t 3 t w h ( x i n ) t w l ( x i n ) 0 . 8 v c c 0.2 v c c x in t c(s clk ) t w l ( s c l k ) t wh(s clk ) 0.2 v c c 0.8 v c c s clk t r t f t d ( s c l k - t x d ) t v(s clk -t x d) t x d r x d 0.2 v cc 0.8 v cc t s u ( r x d - s c l k ) t h ( s c l k - r x d )
76 single-chip 8-bit cmos microcomputer 3822 group mitsubishi microcomputers package outline qfp80-p-1420-0.80 1.58 weight(g) e jedec code eiaj package code lead material alloy 42 80p6n-a plastic 80pin 14 ? ?
single-chip 8-bit cmos microcomputer 3822 group mitsubishi microcomputers ? 2002 mitsubishi electric corp. new publication, effective feb. 2002. specifications subject to change without notice. notes regarding these materials ? these materials are intended as a reference to assist our customers in the selection of the mitsubishi semiconductor product be st suited to the customer s application; they do not convey any license under any intellectual property rights, or any other rights, belonging to mitsubishi electric corporation or a third party. ? mitsubishi electric corporation assumes no responsibility for any damage, or infringement of any third-party s rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. ? all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents info rmation on products at the time of publication of these materials, and are subject to change by mitsubishi electric corporation without notice due to product improvements or other reasons. it is therefore recommended that c ustomers contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. mitsubishi electric corporation assu mes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by mitsubishi electric corporation by various means, including the mitsubish i semiconductor home page (http://www.mitsubishichips.com). ? when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. mitsubishi electric corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. ? mitsubishi electric corporation semiconductors are not designed or manufactured for use in a device or system that is used unde r circumstances in which human life is potentially at stake. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor when considering the use of a product contained herei n for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. ? the prior written approval of mitsubishi electric corporation is necessary to reprint or reproduce in whole or in part these ma terials. ? if these products or technologies are subject to the japanese export control restrictions, they must be exported under a licens e from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is pro hibited. ? please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for further detail s on these materials or the products contained therein. keep safety first in your circuit designs! ? mitsubishi electric corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with a ppropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. head office: 2-2-3, marunouchi, chiyoda-ku, tokyo 100-8310, japan lqfp80-p-1212-0.5 weight(g) C 0.47 jedec code eiaj package code lead material cu alloy 80p6q-a plastic 80pin 12 ?
revision history 3822 group data sheet rev. date description page summary (1/2) 1.0 01/20/98 first edition 2.0 10/23/00 1 1 1 1 1 1 1 2 3 4 5 6 7 7 7 8 8 8 9 9 9 10 10 10 11C13 11 12 12 13 15 17 18 21 22 22 22 22 24 25 26 26 29 30 32 33 33 34 memory size of features is partly revised. serial i/o of features is partly revised. a-d converter of features is added. 2 clock generating circuits of features is partly revised. power source voltage of features is partly revised. power dissipation of features is partly added. product name into figure 1 is revised. product name into figure 2 is revised. figure 3 is partly revised. function of vcc, vss into table 1 is partly revised. function except a port function into table 2 is partly revised. figure 4 is partly revised. explanations of group expansion (standard, one time prom ver- sion, eprom version) are partly revised. figure 5 is partly revised. table 3 is partly revised. explanations of group expansion (extended operating tempera- ture version) are partly revised. figure 6 is partly revised. table 4 is partly revised. group expansion (m version) is added. figure 7 is added. table 5 is added. group expansion (h version) is added. figure 8 is added. table 6 is added. explanations of central processing unit (cpu) are added. figure 9 is added. figure 10 is added. table 7 is added. table 8 is added. figure 12 is partly revised. figure 14 is partly revised. table 9 is partly revised. figure 17 is partly revised. explanations of interrupt control is partly added. explanations of interrupt operation is partly revised. explanations of notes are partly revised. table 9 is partly revised. explanations of key input interrupt (key-on wake up) are partly revised. figure 21 is partly revised. explanations of timer x write control are partly revised. explanations of real time port control are partly revised. figure 25 is partly revised. figure 27 is partly revised. figure 29 is partly revised. explanations of [channel selector] are partly added. explanations of [comparator and control circuit] are partly added. figure 32 is partly revised.
revision history 3822 group data sheet rev. date description page summary (2/2) 35 40 41 41 43 46 47 47 50 52 52 52 52 52 52 54C72 74, 75 figure 33 is partly revised. explanations of clock system output function are partly revised. explanations of reset circuit are partly revised. figure 39 is partly revised. explanations of clock generating circuit are partly eliminated. explanations of decimal calculations are partly eliminated. explanations of data required for mask orders are partly added. table 14 is partly revised. test conditions of i il of p0 0 Cp0 7 , p1 0 Cp1 7 , p3 4 Cp3 7 , p4 0 is added. limit of t c(cntr) into table 21 is revised. limit of t wh(cntr) into table 21 is revised. limit of t wl(cntr) into table 21 is revised. limit of t c(cntr) into table 22 is revised. limit of t wh(cntr) into table 22 is revised. limit of t wl(cntr) into table 22 is revised. tables 25 to 56 are added. package outline is added. 2.0 10/23/00 13 21 22 25 31 44 47 explanations of ?bit 3: decimal mode flag (d) are partly added. figure 17 is partly revised. explanations of notes on interrupts are revised. figure 21 is partly revised. notes on serial i/o is added. figure 44 is partly revised. explanations of data required for mask orders are partly revised. 2.1 01/31/01 2.2 02/28/02 47-48 48 notes on use - countermeasures against noise is added. electric characteristic differences between mask rom and one time prom version mcus is added.

▲Up To Search▲

Price & Availability of M38222M2-XXXHP

	To Download M38222M2-XXXHP Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .